5-5.
SDI Video Interface Section
5-5-1.
CNI-43 Board (XKS-S8110)
The CNI-43 board is a 16-channel input connector board mounted on the rear of this unit.
The cable equalizer circuit and the reclocker circuit on this board correct 16-channel input signal waveforms and outputs
them to the two XPT-38 boards.
Ten CNI-43 boards with 160 inputs are provided in XVS-8000.
5-5-2.
CNI-44 Board (XKS-S8111)
The CNI-44 board has the following functions.
• Converts the format of input video signals from the 16-channel SDI_IN (BNC) connector, performs Primary Color
Collection and Delay processing, and then outputs processed signals to the mother board.
However, the CNI-44 board cannot convert signal formats to a format with different frame rate.
• The following functions can be selected by changing the FPGA (IC1) configuration data.
Outline of functions of each type
- type1: HD to 4K Up-Converter (4 channels)
- type2: SD to HD Up-Converter, Cross-Converter
- type3: Primary_Color_Collection function and Frame_Delay function (16 channels)
- type4: (reserved)
• SDI_IN supports 16 channels and SDI_OUT supports 16 channels for each of A and B. (The B system is available
only for XVS-8000.)
Functions of FPGA (IC1)
SDI signal input
This FPGA converts the serial SDI signal that is input from the BNC connector through the driver IC to parallel signals,
and then sends the parallel signals to the video processor.
SDI output
This FPGA converts parallel signals to which format conversion and video processing have been added to a serial signal,
and then sends the serial signal to the Mother Board connector.
SDI signals of 32 channels (16-channel signals that are directly output from the FPGA + 16-channel signals that are
output through the distributer IC) are output.
DDR control
DDR memory is used for format conversion of video signals.
A DDR memory device consists of four 4GB SO-DIMMs.
Local_Bus communication
This FPGA sends/receives commands and status data to/from the upper CPU through the local bus.
Functions of CADEC (IC2)
FPGA configuration
This CADEC IC configures the FPGA (IC1) by using the selected single-type configuration data from the FLASH_
ROM (IC1803) configuration data by the initialization processing during the power-on process and by switching
configuration data by MENU to make initial settings.
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
5-9
