DVP-68 (1/5)
DDR3
16bit x2
DDR3 MIG #0
Input Freeze
Data Sort
w TBC
SI1/SI2
DDR3
16bit x4
DDR3 MIG #2
Scan Convert
SDI
RX
SDI
RX
Data Sort
w TBC
SI3/SI4
Data Sort
w TBC
SI1/SI2
Video
PROC
Video
PROC
Data Sort
w TBC
SI3/SI4
Pre
VideoH
Modify
HAAF
W
Delay
H2V
Scan
Convert
x IP
Convert
Pre
VideoV
Modify
Mask
Generator
MIG #1
EXT V/K Delay
DDR3
16bit x2
IC6
CPU
MB
CLK
GEN1
FLASH
(1G)x4
FLASH
(512M)x1
IC1
CADEC
MAX10
REFGEN
VAAF
W
Delay
DDR4
16bitx2
x2
Mask
Mixer
Data
Sort
W
Distri
bute
Aurora
TxIF
8B/10B
Aurora
RxIF
8B/10B
Data
Sort
SDI
TX
SDI
RX
Out
Proc
V/K
SVMF_VIF
Data
Sort
w TRS
w PLID
Out
Proc
V/K
Data
Sort
w TRS
w PLID
Out
Proc
V/K
Data
Sort
w TRS
w PLID
Out
Proc
V/K
UVMF_MPC
XPT
Combine
Shadow
Graphics
BKGD
Data
Sort
w TRS
w PLID
SLM_TOP
Dim/Fade
&
Spot
Light1,2,3
SDI
RX
INTP
Lighting
Key Border
SK Gen.
CPUIF
REFGEN
Address Gen
(ZPZ/L Gen)w NL
Aurora
TxIF
8B/10B
HAAF
W
Delay
HDFF
HBF
W
HAAF
VDFF
VBF
W
VAAF
HDFF
HBF
W
HAAF
Pre
VideoH
Modify
H Mask
Gen.
H Mask
Gen.
DDR4
16bitx2
x2
DDR4
16bitx2
x2
DDR4 MIG
Interpolation
DDR4 MIG
Interpolation
DDR4
16bitx2
x2
DDR4
16bitx2
x2
DDR4
16bitx2
x2
DDR4
16bitx2
x2
DDR4
16bitx2
x2
Aurora
RxIF
8B/10B
Data
Sort
PCIe IF
Gen1
Data Buffer
TBC
TBC
TBC
TBC
TBC
TBC
TBC
TBC
TBC
TBC
SDI
TX
SDI
TX
SDI
RX
SDI
RX
SDI
RX
MB
SDI
RX
SDI
RX
CPUIF
MIG #0
Graphics
REFGEN
SDI
TX
SDI
TX
SDI
TX
SDI
TX
SDI
TX
INTP
Lighting
Key Border
SK Gen.
Address Gen
(ZPZ/L Gen)w NL
CPUIF
REFGEN
R_SVM_REC
Recursive
CPUIF
REFGEN
DDR3
16bit x2
MIG #2
Recursive
DDR3
16bit x4
SEL
SEL
Video Block
from MB
V/K SI1
3Gx2
V/K SI2
3Gx2
EXTI
IC2501
IC2502
IC2901
IC2902
IC3001
IC3002
THR
Through
x4 Line
THR
SRC
120
bit
120
bit
LUT
for NL
LUT
for
NL
LUT_BUS[0:3]
6Gx4
6.25Gx4
INTP2_SRC
[0:3]
IC4
FPGA2_2
(SubImage3/4)
EXTVK[0:3] 6Gx4
EFVMI_CH1 6Gx6
VK
VK
PZ
SK
VK
PZ
SK
VK
PZ
SK
VK
PZ
SK
VK
PZ/SK
VK
PZ/SK
VK
PZ/SK
VK
PZ/SK
VK
PZ/SK
VK
PZ/SK
VK
PZ/SK
PZ/SK
VK
VK
PZ/SK
PZ/SK
VK
VK
PZ/SK
PZ/SK
Graphics
Data Bus
EFVMI_CH2 6Gx6
EFVMI_CH3 6Gx6
PCIe Gen1x4(from CPU)
POST2_SRC[0:5]
Z
PZ
L
VK
6Gx6
POST1_SRC[0:5]
6Gx6
SK
Z
PZ
Z
PZ
L
L
VK
VK
SK
SK
Z
PZ
PZ
SK
PZ
SK
SK
L
VK
IC5
FPGA3
VK
VK
120
bit
120
bit
148MHz
IC3
FPGA2_1
(SubImage 1/2)
INTP1_SRC
[0:3]
IC2
FPGA1
6.25G
x4
VM
SRC
MASK
KEY
Main
x4
Line
PRG
PRG
THR
EXTO
EXTI
EXTO
V/K SI3
3Gx2
V/K SI4
3Gx2
from MB
EXTI EXTO
EXTI EXTO
TOF
V1_CLK
REF_CLK
TOF/UI
from CA
Config Bus
to FPGAs
TOF to FPGAs
1000BASE-T
to SCS
PCIe Gen1 4Lane
to FPGA2_2
Local Bus
to FPGAs(CPUIF)
CPU_CLK
CPU_CSn
CPU_Wen
CPU_Oen
CPU_BE[1:0]
DA[31:0]
LBA
: CPU Clock 100MHx
: CPU Chip Select
: CPU Write Enable
: CPU Open(Read)Enable
: CPU Byte Enable[1:0]
: Data[31:0]/Address[25:0]Multiplex
: Address Valid(Active Low)
HD
VD
FD
CKX
EXTVK SI1
3Gx2
EXTVK SI2
3Gx2
EXTVK SI3
3Gx2
EXTVK SI4
3Gx2
X/Y Address
X/Y Address
to MB
to MB
V/K SI1
3Gx2
V/K SI2
3Gx2
V/K SI3
3Gx2
V/K SI4
3Gx2
MON
V/K SI1
3Gx2
MON
V/K SI2
3Gx2
MON
V/K SI3
3Gx2
MON
V/K SI4
3Gx2
EFVMO_CH1
6Gx6
EFVMO_CH2
6Gx6
EFVMO_CH3
6Gx6
IC2601
IC2602
IC6501
IC6502
IC6601
IC6602
IC6701
IC6702
IC6801
IC6802
IC6901
IC6902
IC7001
IC7002
IC7101
IC7102
IC7201
IC7202
IC4501
IC4502
IC4601
IC4602
IC4701
IC4702
IC4801
IC4802
IC4901
IC4902
IC5001
IC5002
IC5101
IC5102
IC5201
IC5202
IC8901
IC8902
IC9001
IC9002
IC8601
IC8602
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
7-19