DVP-68 (2/5)
Debug
CN
CN701
DDR SPD
(SO-DIMM)
T/R
UART0
UART0
IC6
MDIO/MDC
THERMAL
I2C1
I2C2
EEPROM
2Kbit
EEPROM
2Kbit
DDR3 SO-DIMM
2GB(256Mbx64)
CN
IC1502
IC1701
PHY
TRANS
PHY_CLK
LED
CLK Gen
Sys_CCB
JIG Cable
JTAG ICE
CN601
CN751
THRM
IC1664
IC1665
IC1663
I2C
64
RESET_DIMM
DDR
JTAG
Serdes
Port0
0-3
Serdes
Port1
0-3
SD/MMC
JTAG
RGMII
ICE_RSTn to CADEC
ICE_HRESET
ICE_SRESET
ICE_BTWE_RST
ICE_TRST
DDRCLK
125M
PCIe_CLK1
PCIe_CLK2
25M_CLK
PHY_CLK
I2C_CG
SCU_PHY_CTRL
RESET_PHY
CN
(MB)
CN
CN702
Buffer
DIR/OE
Buffer
IC1
CADEC
eLBC
LAD
LALE
Chip Select
LWE[3:0],LOE,LBCTL
CS[3:0]
CTL
WAIT
CTRL
32
AL
Ctl Reg.
EXT
Bus
CTRL
Data/
Address
Sel
ADRS dec.
Config_CS
/WE/OE
Sel
WE
Regen.
LCS[3:0]
CTL
LGTA
IRQ
cfg_xxxx
RSTn
(HRESET/SRESET/TRST)
RSTn_REQ
REF Gen.
INT
Contrl
VD/CKX
Unit ID
Decoder
TOF
From CA-92
UID
P_GOOD
RSTn_REQ
CPU_RSTn(HRESET/SRESET/TRST)
DEV_RESET
RESET_PHY/RESET_DIMM
RST_RCB/RST_PLL/PERST
RST_FLASH
ICE_RSTn
25M_CLK
From CA-92
148.5MHz
27MHz
PCIe_CLK1
PCI-Express Gen1 4Lane
PCIe
IC2/IC3/IC4/IC5
FPGA1/2/3
CPU I/F
CPU_CLK
Data[31:0]
ALE
CSn[3:2]
OEn
WEn
Config
Reset
RESET
From CA-92
FPGA Config
Control
CPU
Config
CTRL
CLOCK
Cleaner
CTRL1
CLOCK
Cleaner
CTRL3
JTAG
CN
CN1601
JTAG
PCIe_CLK2
PERST
IC4 Only
To
FPGA2_2
PCIe
Power
&
Reset
Control
CTRL
Buffer
IC1101
IC1102
IC1103
IC1104
IC1105
Flash_DT
Flash_AD
RST_FLASH
Flash_CS
Flash_Ctl
TOF
INTn_FPGA
CLK
Buffer
DDR_CLK
IC2001
XLX_DT[7:0],CCLKO,
XLX_DONE,
XLX_RPGM,WRITE,
XLX_INIT,CS
SEL
CC_CTRL1
Nor Flash
FPGA Data
1GB
(128Mbyte)
Nor Flash
Boot&Application
512MB
(64Mbyte)
Buffer
IC304
RFSDI_CLK
148.5MHz
CLK
Buffer
IC404
266MHz
I2C_CG
to CLK Gen for P1022
148.5MHz
VID_CLK
FPGA_RST[3:0]
PLL_RST[3:0]
RST_RCB
RST_PLL
Debug
Dipsw
8bit
8
Debug
LED
8bit
8
B-Con
Status
LED
5bit
8
7SEG
LED
16bit
16
Control Block
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
7-20