Functions of CADEC (IC1)
FPGA configuration
This CADEC IC configures the FPGA (IC2, IC3) by using the selected single-type configuration data from the FLASH_
ROM (IC1301, IC1303) configuration data by the initialization processing during the power-on process and by switching
configuration data by MENU to make initial settings.
FLASH_ROM access control
This CADEC IC writes the FPGA configuration data for update that is sent from the upper CPU to the FLASH_ROM
(IC1301, IC1303).
This CADEC IC monitors power status on boards and PLL lock status.
Clock generator control
This CADEC IC controls the clock generator (IC1402).
SDI cable driver control
This CADEC IC controls the SDI cable driver: IC300, IC301, IC302, IC303, IC400, IC401, IC402, IC403, IC500,
IC501, IC502, IC503, IC600, IC601, IC602, and IC603.
Local_Bus communication (CNO-44 board)
This CADEC IC sends/receives commands and status data to/from the upper CPU through the local bus.
I2C communication (CNO-44A board)
This CADEC IC sends/receives commands and status data to/from the upper CPU through the I2C interface.
Functions of FPGA (IC2, IC3)
SDI signal input
This FPGA converts the serial SDI signal that is input from the BNC connector through the cable equalizer IC to parallel
signals, and then sends the parallel signals to the video processor.
SDI output
This FPGA converts parallel signals (to which format conversion and video processing have been added) to a serial
signal, and then sends the serial signal to the cable driver IC.
DDR4 control
DDR4 memory is used for format conversion of video signals.
A DDR4 memory device consists of 16 4GB SDRAM ICs.
Local_Bus communication (CNO-44 board)
This FPGA sends/receives commands and status data to/from the upper CPU through the local bus.
I2C communication (CNO-44A board)
This FPGA sends/receives commands and status data to/from the upper CPU through the I2C interface.
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
5-12
