DVP-68 (3/5)
CPU
IC6
Buffer
IC815
Ether PHY
IC1701
3.3V->1.8V
CLK Buffer
IC306
CLK Buffer
IC305
CLK Buffer
IC306
CLK Buffer
IC404
CLK Cleaner
IC304
Buffer
IC811
SO-DIMM
CN751
SD-Card
CN702
MB
VCLK_P/N
(148.35MHz
148.5MHz)
OSC
X1502
25MHz
CLK Gen.
IC1502
OSC
X301
50MHz
OSC
X2002
156.25
MHz
Buffer
IC301
CADEC
IC1
FPGA1
IC2
FPGA2-1
IC3
FPGA2-2
IC4
FPGA3
IC5
CLK Buffer
IC2002
CLK Buffer
IC2003
OSC
X2003
233.33
MHz
CLK Buffer
IC2001
OSC
X2004
266.66
MHz
Sys CCB
DDRCLK
125M
REF1
REF2
OUT0
OUT1
RFCLK_CADECP/N
RFCLK1P/N
RFCLK2P/N
RFCLK3P/N
RFCLK4P/N
RFCLK5P/N
RFCLK6P/N
RFCLK7P/N
RFCLK8P/N
CL303/304
VID_SEL
By CADEC(Default IN1)
VIDCLK1P/N
VIDCLK2P/N
VIDCLK3P/N
VIDCLK4P/N
RFCLK9P/N
RFCLK10P/N
RFCLK11P/N
RFCLK12P/N
RFCLK13P/N
CL305/306
OUT3
OUT4
OUT0
IN1
MCK0P/N
TP802
CPU_CLK
62.5MHz
3.3V->1.8V
1.8V
MCK1P/N
SDHC CLK
TSEC RX CLK
FPGA2_PCIE_CLKP/N to FPGA2-2 IC4(Bank225)
Reserve
25M_CADEC
TSEC TX CLK
PCIE LR0
PCIE LR1
PCIE LR2
FPGA_CPU_CLK[3]
to FPGA3 IC5(Bank52)
TP301
CPU_CLK CADEC
RFCLK_CADECP/N
25M_CADEC
AURORA_CLK1_P/N
DDR3_SYSCLK3P/N
IN0
for DDR3
for DDR4
IN1
DDR3_SYSCLK1P/N
DDR3_SYSCLK2P/N
DDR4_SYSCLK4P/N
DDR4_SYSCLK3P/N
DDR4_SYSCLK2P/N
DDR4_SYSCLK1P/N
DDR4_SYSCLK6P/N
DDR4_SYSCLK5P/N
DDR4_SYSCLK8P/N
DDR4_SYSCLK7P/N
DDR3_SYSCLK4P/N
to FPGA3 IC5(Bank44)
DDR3_SYSCLK5P/N
to FPGA3 IC5(Bank73)
FPGA1_CPU_CLK[0]
VID_CLK1P/N
FPGA2_CPU_CLK[0]
VID_CLK2P/N
FPGA2_CPU_CLK[1]
DDR3_SYSCLK5P/N
DDR3_SYSCLK4P/N
VID_CLK3P/N
FPGA1_CPU_CLK[0]
VID_CLK4P/N
RFCLK3P/N
BANK133
BANK132
BANK131
BANK73
BANK72
BANK71
DDR3
64bit
DDR3
32bit
DDR3
32bit
CPUIF
REF
BANK68
BANK67
BANK66
BANK53
BANK52
BANK51
BANK46
BANK45
BANK44
BANK70
BANK65
AURORA
No used
SDI 6G
SDI 3G
BANK128
BANK127
BANK126
BANK233
BANK232
BANK231
BANK230
BANK229
BANK228
BANK227
BANK226
BANK225
BANK224
RFCLK1P/N
RFCLK2P/N
RFCLK6P/N
RFCLK4P/N
RFCLK5P/N
RFCLK9P/N
RFCLK7P/N
RFCLK8P/N
RFCLK13P/N
RFCLK12P/N
RFCLK10P/N
RFCLK11P/N
AURORA_CLK2_P/N
AURORA_CLK3_P/N
FPGA2_PCIE_CLK_P/N
AURORA_CLK2_P/N
to FPGA2-1 IC3(Bank226)
AURORA_CLK3_P/N
to FPGA2-2 IC4(Bank226)
for Aurora
FPGA_CPU_CLK[2]
to FPGA2-2 IC4(Bank70)
FPGA_CPU_CLK[1]
to FPGA2-1 IC3(Bank70)
FPGA_CPU_CLK[0]
to FPGA1 IC2(Bank52)
CPU_CLK_CADEC
to CADEC IC1
INTP_DDR_CLK_SEL
By CADEC(Default IN1)
BANK133
BANK132
BANK131
No used
Test
SDI 6G
SDI 6G
AURORA
PCle
BANK128
BANK127
BANK126
BANK233
BANK232
BANK231
BANK230
BANK229
BANK228
BANK227
BANK226
BANK225
BANK224
BANK73
BANK72
BANK71
DDR4
32bitx2
DDR4
32bitx2
DDR4
32bitx2
DDR4
32bitx2
CPUIF
REF
BANK68
BANK67
BANK66
BANK53
BANK52
BANK51
BANK46
BANK45
BANK44
BANK70
BANK65
BANK133
BANK132
BANK131
BANK73
BANK72
BANK71
DDR3
64bit
No Used
DDR3
32bit
CPUIF
REF
BANK68
BANK67
BANK66
BANK53
BANK52
BANK51
BANK46
BANK45
BANK44
BANK70
BANK65
SDI 6G
SDI 6G
SDI 6G
SDI 6G
SDI 3G
BANK128
BANK127
BANK126
BANK233
BANK232
BANK231
BANK230
BANK229
BANK228
BANK227
BANK226
BANK225
BANK224
BANK133
BANK132
BANK131
No used
Test
SDI 6G
SDI 6G
AURORA
PCle
BANK128
BANK127
BANK126
BANK233
BANK232
BANK231
BANK230
BANK229
BANK228
BANK227
BANK226
BANK225
BANK224
BANK73
BANK72
BANK71
DDR4
32bitx2
DDR4
32bitx2
DDR4
32bitx2
DDR4
32bitx2
CPUIF
REF
BANK68
BANK67
BANK66
BANK53
BANK52
BANK51
BANK46
BANK45
BANK44
BANK70
BANK65
Clock Tree Block
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
7-21