CNO-45 (1/2)
BUF
BUF
IC900
CND1
CADEC
LOCAL BUS
RESET
FPGA_A
FPGA_B
D801
PWR
D802
CFG
D800
PLL
D1000
CAD
D2401
RED
D2402
GRN
D2601
F_A
D3701
RED
D3702
GRN
D3901
F_B
S2401
74MHz
148MHz
296MHz
FLASH
1G
FLASH
1G
IC1301 IC1303
SDI-IN9
~SDI-IN16
BUF
EPR2
IC1001
CN1000
RESET
GEN
S1000
RE_CONFIG
IC1005
CNM1
CNF1
SDI-IN9
~SDI-IN16
SDI-IN1
~SDI-IN8
SDI-IN1
~SDI-IN8
CNM1
CNF1
SDI-OUT1
~SDI-OUT8
74MHz
296MHz
S3701
JTAG
IC2
IC3
CNF1
VCLK
CLK
GEN
IC1402
VCLK2
CLK
BUF
CLK
BUF
CLK
BUF
CLK CTRL
74MHz
148MHz
296MHz
D1400
STS1
D1401
STS0
100MHz
BUF
IC901
BUF
IC902
IC1403,
IC1404
IC1405,
IC1406
266MHz
CNB1
SLOT NO.
I2C
NET485
BD EXIST
S800
BUF
IC1000
BUF
IC1004
CPU_CLOCK
SYS_RESET
CONFIG
CONF_DONE
CONF_DONE
TOF
266MHz
MLVDS
MLVDS
Board
Suffix
R848,R849
SDI
RX
FORMAT
CONVERTER
OUTPUT
PROCESS
SEL
SDI
TX
SDI
RX
FORMAT
CONVERTER
OUTPUT
PROCESS
SEL
SDI
TX
X1301
100MHz
100MHz
X'tal
CLOCK
BUF
IC1302
100MHz
100MHz
CN301
CN302
IC905
BUF
BUF
IC1008,IC1009
IC1006,IC1007
BUF
BUF
IC1102,IC1103
IC1202,IC1203
100MHz
IC1
100MHz
148MHz
LOCAL BUS
IC1400,
IC1401
MLVDS
MLVDS
from/to IC2
from/to IC3
CPUCLK(100MHz)
TOF
74MHz
to CADEC (IC1)
to FPGA_A (IC2)
to FPGA_B (IC3)
PG_+1.2V-C
PG_+1.8V-C
PG_+2.5V-C
PG_+0.95V-FA
PG_+0.95V-FB
PG_+1.03V-FA
PG_+1.03V-FB
PG_+1.8V-FA1
PG_+1.8V-FB1
PG_GP3_FA
PG_GP3_FB
PG_GP1
SDI-OUT9
~SDI-OUT16
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
7-15