The Nios processor has the following main functions.
• Control for FPGA’s peripheral devices (temperature sensor, EEPROM, and clock device).
• NeptuneII control
• Network PHY control
• Data communication (of recording/updating set values, error report, etc.) with the IP Live System Manager
• Data communication with the upper CPU (on the CA-92 board) through the RS-485 interface
NeptuneII
The main CPU of NeptuneII runs on the Linux OS. The NeptuneII firmware is stored in the eMMC (IC1507, IC1907,
IC2403, IC2404) and works with the DDR3 (IC1401, IC1801, IC3401, IC3801) as work RAM.
The NeptuneII CPU has the following main functions.
• FEC, LLVC Encode/Decode, Network Packetize, and network synchronization
• Data communication with the IP Live System Manager
• Data communication with the Host CPU (Nios2)
CADEC
FPGA configuration
The FPGA configuration data is stored in the flash memory (IC402, IC403, IC2403, IC2404). After power is turned on,
the CADEC (IC301, IC2301) reads necessary data from the flash memory and configures the FPGA.
Nios boot
After the configuration has been completed, the CADEC releases the FPGA reset to boot the Nios.
Writing installation data
Installation data used in the production process is written to the flash memory (IC402, IC403, IC2403, IC2404) through
the local bus connected to the CA-92 board.
5-6-3.
NET-42 Board (XKS-C9111, XKS-C9121, XKS-C9111N, XKS-C9121N)/
NET-42A Board (XKS-C8111)/ NET-42B Board (XKS-C8166)
The NET-42 board, NET-42A board, and the NET-42B board have the following functions.
• These boards function as a network interface board that supports Video Over IP.
• These boards convert the SDI signal in the switcher to an IP signal by using the FPGA.
• The external interface supports QSFP28 (conforming to 100GBASE-SR) and is provided with a cage for mounting
the QSFP28 module.
• The NET-42 board (XKS-C9111, XKS-C9111N) and the NET-42A board (XKS-C8111) are used to input video
signals.
• The NET-42B board (XKS-C8166) is used to output video signals.
• The NET-42 board (XKS-C9121, XKS-C9121N) is used to input and output video signals.
• In the XKS-C9111N/XKS-C9121N, the 4th lane of the QSFP + (25 Gb Ex 4 lane) transceiver is not used.
Video signal processor
Network input (NET-42 board [XKS-C9111, XKS-C9121, XKS-C9111N, XKS-C9121N],
NET-42A board [XKS-C8111])
The IP signal (conforming to 100GBASE-SR) from the QSFP28 module is converted to an IP (RTP) signal by using
the FPGA (IC003, IC001), and then the converted IP (RTP) signal is transmitted to the FPGA (IC004, IC002) through
the Aurora interface. This signal is corrected to the REF signal of the unit in the TBC circuit, and is then converted to
a serial signal. This serial signal is output to the switcher as an SDI signal.
Network output (NET-42 board [XKS-C9121, XKS-C9121N], NET-42B board [XKS-C8166])
The SDI signal transmitted from the switcher to the FPGA (IC004, IC002) is converted to an IP (RTP) signal, and then
the converted IP (RTP) signal is transmitted to the FPGA (IC003, IC001) through the Aurora interface. The IP (RTP)
XVS-9000-C/XVS-8000-C/XVS-7000-C/XVS-6000-C
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