
4.1.17 USART SPI
SPI Master Timing
Table 4.28. SPI Master Timing
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK period
t
SCLK
2 *
t
HFPERCLK
—
—
ns
t
CS_MO
0
—
8
ns
SCLK to MOSI
t
SCLK_MO
3
—
20
ns
MISO setup time
t
SU_MI
IOVDD = 1.62 V
56
—
—
ns
IOVDD = 3.0 V
37
—
—
ns
t
H_MI
6
—
—
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of V
DD
(figure shows 50% of V
DD
)
CS
SCLK
CLKPOL = 0
MOSI
MISO
t
CS_MO
t
H_MI
t
SU_MI
t
SCKL_MO
t
SCLK
SCLK
CLKPOL = 1
Figure 4.1. SPI Master Timing Diagram
BGM11S Blue Gecko
Bluetooth
®
SiP Module Data Sheet
Electrical Specifications
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