CPU modules
4.2 CPU module CPU550/CPU551
SIMATIC TDC hardware
98
System Manual, 08/2017, A5E01114865-AL
Memory
CPU
6DD1600-0BA1
6DD1600-0BA2
6DD1600-0BA3
SDRAM / DDR2-DRAM
•
During initialization, the user program is loaded from
program memory and expanded (Boot Flash is available
separately)
•
Data memory for the operating system, communication,
message buffer, and Trace
32 MB
128 MB
1 GB
SRAM
Buffered SRAM (by means of external battery in the rack)
contains the following data that must be backed up to reten-
tive memory on power failure:
•
Fault diagnostics of the operating system ("exception
buffer")
•
Max. 993 process variables configured with SAV func-
tion block
•
Data recorded using the Trace function or the message
system (SRAM can be optionally configured)
256 KB
512 KB
512 KB
Synchronized L1 cache
64 KB
64 KB
64 KB
Synchronized L2 cache
ext. L2 cache
int. L2 cache
512 KB
256 KB
512 KB
Synchronized L3 cache
ext. L3 cache
int. L3 cache
2 MB
8 MB
1 MB
Module slots
Number
3
Allocation of the slots
•
Program memory MC5xx
•
PMC plug-in cards
1)
1)
PMC plug-in cards are currently not provided.
Time
Resolution
0.1 ms
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