Glossary
S7-1500R/H redundant system
System Manual, 10/2018, A5E41814787-AA
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System states
The system states of the S7-1500R/H redundant system result from the operating states of
the primary and backup CPU. The term system state is used as a simplified expression that
refers to the operating states that occur simultaneously on both CPUs. The S7-1500R/H
redundant system has the system states STOP, STARTUP, RUN-Solo, SYNCUP and RUN-
Redundant.
System IP address
In addition to the device IP addresses of the CPUs, the redundant system S7-1500R/H
supports system IP addresses:
●
System IP address for the X1 PROFINET interfaces of the two CPUs (system IP address
X1)
●
System IP address for the X2 PROFINET interfaces of the two CPUs (system IP address
X2)
You use the system IP addresses for communication with other devices (for example, HMI
devices, CPUs, PG/PC). The devices always communicate over the system IP address with
the primary CPU of the redundant system. This ensures that the communication partner can
communicate with the new primary CPU (previously backup CPU) in the RUN-Solo system
state after failure of the original primary CPU in redundant operation.
TIA Portal
Totally Integrated Automation Portal
The TIA Portal is the key to the full performance capability of Totally Integrated Automation.
The software optimizes operating, machine and process sequences.
Time-delay interrupt
You will find further information in the glossary entry "Interrupt, time-delay".
Time-of-day interrupt
You will find further information in the glossary entry "Interrupt, time-of-day".
Timer
Timers are components of the system memory of the CPU. The operating system
automatically updates the content of the "timer cells" asynchronously to the user program.
STEP 7 instructions define the precise function of the timer cell (for example on-delay) and
trigger its execution.
Update interrupt
You will find further information in the glossary entry "Interrupt, update".
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