Controllers
6.2 Drive functions
AT40, ATD400V, ATD400K, ATD4xxW, ATD400S, ATE250S, ATD400T
System Manual, 06/2016, A2B00096162-AN
89
Drive orders
In parallel with logical signal combination, a drive order can be assigned to the Q outputs.
Door commands that are assigned to the outputs are only active as long as the assigned
output is active (jog mode). A drive order is composed of a door command "DCMD" and an
optional door command expansion bit "DCMD expansion".
Drive order = door c door command expansion bit
Both commands are expressed as 16-bit values. The structure of the DCMD and DCMD
expansion bit fields corresponds to the technology control world 1 (TSW 1) signals of the
same names, see Table 6-73 Technology control word 1 (TSW1) (Page 206). The "LB" and
"DCOPS" and expansion bits are not evaluated here.
15 … 8
7
6
5
4
3
2
1
0
DCMD
DCMD expansion
Example
●
The value 0x0301
hex
corresponds to the "close slowly" drive order.
●
The value 0x0215
hex
corresponds to the "slow, partial opening in NDG mode" drive order.
The default command mode is defined by the p100 "DefCmdMode" parameter. The default
factory setting is for command issuing via the bus system to be active (exception:
ATD401W). This means that the drive orders of the FBLOCK system are only valid in the
drive state "S4: Z_OPERATION" (see Image 6-33 Sequential control state graph
(Page 216)).
Note
If the controller is to be operated without a bus connection (offline), default command issuing
must be diverted → p100 "DefCmdMode" = 2 (FBLOCK).
You will find more detailed information in Section Drive orders (Page 94).
Parallel drive orders
Door commands that are active during a processing cycle are assigned the following
priorities:
●
Stop > Open > Close
All other door commands are determined on the basis of the processing sequence.
Parallel door command expansion bits
The door command expansion bits that are active during a processing cycle are combined
(logically ORed).
