3.3 : XMC Connectors
This section details the signals on the XMC connectors as implemented on the VP3500.
3.3.1 : XMC 1
There are two connectors for XMC site 1 on the VP3500. J15 has the standard XMC PCIe signals (VITA
42.3) and J16 has the user defined IO signals which are dependent on what the XMC card supports.
The J16 IO signals are routed to the backplane connectors P3 & P4 per VITA 46.9 (X38s+X12d+X8d).
Compare Tables 13 & 14 to Table 10 below for J16 to see how these IO signals are mapped.
The following tables show the pinout for the XMC 1 connectors.
Pin
Row A
Row B
Row C
Row D
Row E
Row F
1
DP1_T0-
+3_3V
DP1_T1-
VPWR
2
GND
GND
TRST_L
GND
GND
RESET_L
3
DP1_T2-
+3_3V
DP1_T3-
VPWR
4
GND
GND
TCK
GND
GND
MRSTO_L
5
DP1_T4-
+3_3V
DP1_T5-
VPWR
6
GND
GND
TMS
GND
GND
+12V_AUX
7
DP1_T6-
+3_3V
DP1_T7-
VPWR
8
GND
GND
TDI
GND
GND
-12V_AUX
9
NC
NC
NC
NC
NC
VPWR
10
GND
GND
TDO
GND
GND
GA0
11
DP1_R0-
MBIST_L
DP1_R1-
VPWR
12
GND
GND
GA1
GND
GND
PRSNT_L
13
DP1_R2-
+3_3V_AUX
DP1_R3-
VPWR
14
GND
GND
GA2
GND
GND
I2C_DAT
15
DP1_R4-
NC
DP1_R5-
VPWR
16
GND
GND
NVMRO
GND
GND
I2C_CLK
17
DP1_R6-
NC
DP1_R7-
NC
18
GND
GND
NC
GND
GND
NC
19
CLK_REF-
NC
WAKE_L
NC
NC
Table 9 : XMC 1 J15 Signals
DP1
These signals make up the 1x8 PCIe port from the main PCIe switch to XMC 1. This port supports Gen
2 speeds (5GT/s) but will train to Gen 1 and also to reduced lanes if required by the XMC module.
VP3500 User Manual • Document Number 101-3500-0001 • Revision A0
Property of Rigel Engineering, LLC. Confidential & Proprietary
690 Cone Park Court, Merritt Island, Florida 32952
page 39