Renesas M16C/60 Series, Руководство пользователя

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R01UH0136EJ0210 Rev.2.10 Page 83 of 800
Jul 31, 2012
M16C/64A Group 8. Clock Generator
8. Clock Generator
8.1 Introduction
The clock generator generates operating clocks for the CPU and peripheral functions. The following
circuits are incorporated to generate the system clock signals.
•
Main clock oscillator
•
PLL frequency synthesizer
•
125 kHz on-chip oscillator
•
Sub clock oscillator
Table 8.1 lists the specifications of the clock generator, and Figure 8.1 shows the block diagram of system
clock generator.
Table 8.1 Clock Generator Specifications
Note:
1. The PLL frequency synthesizer uses the main clock oscillator as a reference clock source. The items
above are based on the main clock oscillator.
Item
Main Clock
Oscillator
PLL Frequency
Synthesizer
125 kHz on-chip oscillator Sub Clock Oscillator
Application
•
CPU clock source
•
Peripheral function
clock source
•
CPU clock source
•
Peripheral
function clock
source
•
CPU clock source
•
Peripheral function clock
source
•
CPU and peripheral function
clock sources when the
main clock stops oscillating
•
Watchdog timer count
source when the CPU clock
is stopped
•
CPU clock source
•
Peripheral function
clock source
Clock
frequency
f(XIN) f(PLL) fOCO-S f(XCIN)
Connectable
oscillators •
Ceramic resonator
•
Crystal
-
(see note 1)
-
Crystal
Pins connecting
to oscillator
XIN, XOUT -
(see note 1)
- XCIN, XCOUT
Oscillator
start/stop function
Enabled Enabled Enabled Enabled
Oscillator status
after reset
Oscillating Stopped Oscillating Stopped
Other An externally
generated clock can
be input.
-
(see note 1)
- An externally
generated clock can
be input.