Renesas Hitachi H8S/2191, Руководство по оборудованию, Страница: 789 / 1065

Rev. 2.0, 11/00, page 762 of 1037
(9) Bit Pattern Register (BTPR)
0
1
1
1
R/W
*
2
1
R/W
*
3
1
4 5
1
6 7
R/W
*
R/W
*
R/W
*
LSP5
1
R/W
*
LSP4
1
R/W
*
LSP6
1
R/W
*
LSP7 LSP3 LSP2 LSP1 LSP0
Note: * Write is prohibited when bit pattern detection is selected.
Bit :
Initial value :
R/W :
The bit pattern register (BTPR) is an 8-bit shift register which detects and records the bit pattern
of the CTL pulses. If a CTL pulse is detected in PB or ASM mode, the register is shifted
leftward at the rising edge of PB-CTL, and reflects the determined result of long/short on bit 0
(long pulse = 1, short pulse = 0).
If the BPON bit is set to 1 in PB mode, the register starts detection of bit pattern immediately
after the CTL pulse. To exit the bit pattern detection, set the BPON bit at 0.
If 1 was written in the BPS bit when the bit pattern is being detected, the BPF bit is set at 1 when
an 8-bit bit pattern was detected. If continuous detection of 8-bits is required, write 0 in the BPF
bit, and then write 1 in the BPS bit.
At the time of VISS detection, the bit pattern detection is disabled. Set the BPON bit to 0 at the
time of VISS detection.
In REC mode, the register records the long/short in the bit pattern set in BTPR. The pulse in
record mode is determined always by bit 7 (LSP7) of BTPR. BTPR records one pulse, shifts
leftward, and stores the data of bit 7 to bit 0.
BTPR is initialized to H'FF by a reset, stand-by, module stop, or CTL stop.