Section 2 CPU
Rev. 3.00 Mar. 14, 2006 Page 54 of 804
REJ09B0104-0300
2.8
Addressing Modes and Effective Address Calculation
The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a
subset of these addressing modes.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.12 Addressing Modes
No. Addressing
Mode
Symbol
1 Register
direct
Rn
2 Register
indirect
@ERn
3
Register indirect with displacement @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)
4
Index register indirect with displacement @(d:16,
RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L)
@(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)
5
Register indirect with post-increment
@ERn
+
Register indirect with pre-decrement
@
−
ERn
Register indirect with pre-increment
@
+
ERn
Register indirect with post-decrement
@ERn
−
6 Absolute
address
@aa:8/@aa:16/@aa:24/@aa:32
7 Immediate
#xx:3/#xx:4/#xx:8/#xx:16/#xx:32
8 Program-counter
relative @(d:8,PC)/@(d:16,PC)
9
Program-counter relative with index register @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)
10 Memory
indirect
@@aa:8
11
Extended memory indirect
@@vec:7
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