Renesas H8SX series, Руководство по оборудованию

Страница: 164 / 846

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar. 14, 2006 Page 126 of 804
REJ09B0104-0300
6.2 Register Descriptions
The bus controller has the following registers.
•
Bus control register 2 (BCR2)
6.2.1 Bus Control Register 2 (BCR2)
BCR2 is used for bus arbitration control of the CPU and DMAC, and enabling/disabling of the
write data buffer function to the peripheral device.
Bit
Bit Name
Initial Value
R/W
7
—
0
R
6
—
0
R
5
—
0
R/W
4
IBCCS
0
R/W
3
—
0
R
2
—
0
R
1
—
1
R/W
0
PWDBE
0
R/W
Bit Bit Name
Initial
Value R/W Description
7, 6

All 0 R Reserved
These are read-only bits and cannot be modified.
5

0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
4 IBCCS 0 R/W Internal Bus Cycle Control Select
Selects the internal bus arbiter function.
0: Releases the bus mastership according to the priority
1: Executes the bus cycles alternatively when a CPU
bus mastership request conflicts with a DMAC bus
mastership request
3, 2

All 0 R Reserved
These are read-only bits and cannot be modified.
1

1 R/W Reserved
This bit is always read as 1. The write value should
always be 1.
0 PWDBE 0 R/W Peripheral Module Write Data Buffer Enable
Specifies whether or not to use the write data buffer
function for the peripheral module write cycles.
0: Write data buffer function not used
1: Write data buffer function used
Downloaded from Elcodis.com electronic components distributor