Rev. 3.00 Mar. 14, 2006 Page xxxiv of xxxviii
Table 5.2
Interrupt Sources, Vector Address Offsets, and Interrupt Priority........................ 105
Table 5.3
Interrupt Control Modes ....................................................................................... 112
Table 5.4
Interrupt Response Times ..................................................................................... 117
Table 5.5
Number of Execution States in Interrupt Handling Routine ................................. 118
Table 5.6
Interrupt Source Selection and Clear Control ....................................................... 119
Table 5.7
CPU Priority Control ............................................................................................ 121
Table 5.8
Example of Priority Control Function Setting and Control State ......................... 121
Section 6 Bus Controller (BSC)
Table 6.1
Synchronization Clocks and Their Corresponding Functions............................... 128
Table 6.2
Number of Access Cycles for On-Chip Memory Spaces...................................... 129
Table 6.3
Number of Access Cycles for Registers of On-Chip Peripheral Modules ............ 129
Section 7 DMA Controller (DMAC)
Table 7.1
Data Access Size, Valid Bits, and Settable Size ................................................... 142
Table 7.2
Settings and Areas of Extended Repeat Area ....................................................... 156
Table 7.3
Transfer Modes..................................................................................................... 157
Table 7.4
List of On-chip module interrupts to DMAC........................................................ 167
Table 7.5
Priority among DMAC Channels.......................................................................... 181
Table 7.6
Interrupt Sources and Priority............................................................................... 200
Section 8 I/O Ports
Table 8.1
Port Functions....................................................................................................... 205
Table 8.2
Register Configuration in Each Port ..................................................................... 210
Table 8.3
Input Pull-Up MOS State...................................................................................... 214
Table 8.4
Available Output Signals and Settings in Each Port............................................. 239
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.1
Unit Configuration for Each Product.................................................................... 252
Table 9.2
TPU Functions (Unit 0) ........................................................................................ 252
Table 9.3
TPU Functions (Unit 1) ........................................................................................ 254
Table 9.4
Pin Configuration.................................................................................................. 258
Table 9.5
CCLR2 to CCLR0 (Channels 0 and 3) ................................................................. 266
Table 9.6
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5) ........................................................ 266
Table 9.7
Input Clock Edge Selection .................................................................................. 267
Table 9.8
TPSC2 to TPSC0 (Channel 0) .............................................................................. 267
Table 9.9
TPSC2 to TPSC0 (Channel 1) .............................................................................. 267
Table 9.10
TPSC2 to TPSC0 (Channel 2) .............................................................................. 268
Table 9.11
TPSC2 to TPSC0 (Channel 3) .............................................................................. 268
Table 9.12
TPSC2 to TPSC0 (Channel 4) .............................................................................. 269
Table 9.13
TPSC2 to TPSC0 (Channel 5) .............................................................................. 269
Table 9.14
MD3 to MD0 ........................................................................................................ 271
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