Renesas H8SX series, Руководство по оборудованию

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Section 6 Bus Controller (BSC)
Rev. 3.00 Mar. 14, 2006 Page 130 of 804
REJ09B0104-0300
6.6 Write Data Buffer Function
6.6.1 Write Data Buffer Function for Peripheral Module
This LSI has a write data buffer function for the peripheral module. Using the write data buffer
function enables external writes and on-chip memory accesses in parallel. The write data buffer
function is made available by setting the PWDBE bit in BCR2 to 1.
Figure 6.3 shows an example of the timing when the write data buffer function is used. When this
function is used, if a peripheral module write continues for two cycles or longer, and there is an
internal access next, only the peripheral module write is executed in the first two cycles. However,
from the next cycle onward, on-chip memory accesses and the external address space write rather
than waiting until it ends are executed in parallel.
Peripheral module write
I
φ
Internal address bus
Internal peripheral
address bus
Internal peripheral
data bus
Peripheral module address
P
φ
On-chip
memory
read
Figure 6.3 Example of Timing when Write Data Buffer Function is Used
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