Renesas H8SX series, Руководство по оборудованию

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Section 20 List of Registers
Rev. 3.00 Mar. 14, 2006 Page 710 of 804
REJ09B0104-0300
Register Name Abbr.
Number
of Bits
Address Module
Data
Width
Access
Cycles
(Read/Write)
Timer counter_2 TCNT_2 16 H'FFFE6 TPU_2
*
2
16 2P
φ
/2P
φ
Timer general registerA_2 TGRA_2 16 H'FFFE8 TPU_2 *
2
16 2P
φ
/2P
φ
Timer general registerB_2 TGRB_2 16 H'FFFEA TPU_2
*
2
16 2P
φ
/2P
φ
Timer control register_3 TCR_3 8 H'FFFF0 TPU_3
*
2
16 2P
φ
/2P
φ
Timer mode register_3 TMDR_3 8 H'FFFF1 TPU_3 *
2
16 2P
φ
/2P
φ
Timer I/O control register H_3 TIORH_3 8 H'FFFF2 TPU_3 *
2
16 2P
φ
/2P
φ
Timer I/O control register L_3 TIORL_3 8 H'FFFF3 TPU_3
*
2
16 2P
φ
/2P
φ
Timer interrupt enable
register_3 TIER_3 8 H'FFFF4 TPU_3 *
2
16 2P
φ
/2P
φ
Timer status register_3 TSR_3 8 H'FFFF5 TPU_3
*
2
16 2P
φ
/2P
φ
Timer counter_3 TCNT_3 16 H'FFFF6 TPU_3
*
2
16 2P
φ
/2P
φ
Timer general register A_3 TGRA_3 16 H'FFFF8 TPU_3 *
2
16 2P
φ
/2P
φ
Timer general register B_3 TGRB_3 16 H'FFFFA TPU_3
*
2
16 2P
φ
/2P
φ
Timer general register C_3 TGRC_3 16 H'FFFFC TPU_3
*
2
16 2P
φ
/2P
φ
Timer general register D_3 TGRD_3 16 H'FFFFE TPU_3 *
2
16 2P
φ
/2P
φ
Notes: 1. The lower 20 bits are indicated.
2. Supported only by the H8SX/1527.
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