Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar. 14, 2006 Page 182 of 804
REJ09B0104-0300
7.4.9
DMA Basic Bus Cycle
Figure 7.23 shows an examples of signal timing of a basic bus cycle. In figure 7.23, data is
transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When
the bus mastership is passed from the DMAC to the CPU, data is read from the source address and
it is written to the destination address. The bus is not released between the read and write cycles
by other bus requests. DMAC bus cycles follows the bus controller settings.
CPU cycle
DMAC cycle (one word transfer)
CPU cycle
Address bus
B
φ
T1
T2
T1
T2
T3
T1
T2
T3
Source address
Destination address
RD
High
HHWR
,
HLWR
,
LHWR
LLWR
Figure 7.23 Example of Bus Timing of DMA Transfer
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