Section 14 Synchronous Serial Communication Unit (SSU)
Rev. 3.00 Mar. 14, 2006 Page 534 of 804
REJ09B0104-0300
(3)
Data Reception
Figure 14.7 shows an example of reception operation, and figure 14.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the
SCS
pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
electronic components distributor
Содержание H8SX series
Страница 2: ...Rev 3 00 Mar 14 2006 Page ii of xxxviii Downloaded from Elcodis com electronic components distributor...
Страница 22: ...Rev 3 00 Mar 14 2006 Page xxii of xxxviii Downloaded from Elcodis com electronic components distributor...
Страница 32: ...Rev 3 00 Mar 14 2006 Page xxxii of xxxviii Downloaded from Elcodis com electronic components distributor...
Страница 38: ...Rev 3 00 Mar 14 2006 Page xxxviii of xxxviii Downloaded from Elcodis com electronic components distributor...
Страница 845: ...Downloaded from Elcodis com electronic components distributor...
Страница 846: ...H8SX 1520 Group Hardware Manual Downloaded from Elcodis com electronic components distributor...