Renesas H8/38024 Series, Руководство по оборудованию

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Rev. 6.00, 08/04, page 525 of 628
A.3 Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I • S
I
+ J • S
J
+ K • S
K
+ L • S
L
+ M • S
M
+ N • S
N
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
S
I
= 2, S
L
= 2
Number of states required for execution = 2 • 2 + 2 • 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
S
I
= S
J
= S
K
= 2
Number of states required for execution = 2 • 2 + 1 • 2+ 1 • 2 = 8
Table A.3 Number of Cycles in Each Instruction
Access Location
Execution Status
(instruction cycle)
On-Chip Memory On-Chip Peripheral Module
Instruction fetch S
I
2 —
Branch address read S
J
Stack operation S
K
Byte data access S
L
2 or 3
*
Word data access S
M
—
Internal operation S
N
1
Note:
*
Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data Access
for details.