Rev. 6.00, 08/04, page 54 of 628
2.6
Basic Operational Timing
CPU operation is synchronized by a system clock (
φ
) or a subclock (
φ
SUB
). For details on these
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of
φ
or
φ
SUB
to
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
T
1
state
Bus cycle
T
2
state
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Read data
Address
Write data
Internal data bus
(write access)
φ
or
φ
SUB
Figure 2.11 On-Chip Memory Access Cycle
Содержание H8/38024 Series
Страница 18: ...Rev 6 00 08 04 page xviii of xxx...
Страница 30: ...Rev 6 00 08 04 page xxx of xxx...
Страница 130: ...Rev 6 00 08 04 page 100 of 628...
Страница 216: ...Rev 6 00 08 04 page 186 of 628...
Страница 416: ...Rev 6 00 08 04 page 386 of 628...
Страница 432: ...Rev 6 00 08 04 page 402 of 628...
Страница 468: ...Rev 6 00 08 04 page 438 of 628...
Страница 661: ...H8 38024 H8 38024S H8 38024F ZTAT H8 38124 Group Hardware Manual...