PSI System Controls and Diagnostics
A500 User Manual
A500_UM_090115 Page 11 of 61
7
Specification
Processor
ADSP 21160 high performance 32 bit floating point SHARC
processor
Processor clock
80 MHz
External bus
20 MHz
Floating point speed
480 MFlops peak, 320 Mflops sustained (FIR algorithm)
On-chip memory
4 Mb x1 for program and data (max 87Kb x48 program or 128Kb
x32 data)
Operating system
Analog Devices VDK real time
Development environment
Analog Devices Visual DSP C++ version 4.5
External SRAM
8 Mb x 32, zero wait
NVR
512 kb x 8 battery-backed RAM
Program memory
4 Mb x 16 flash
Bootloader memory
512 kb x 8 demountable flash (MW29W040B PLCC)
I/O ports
Two internal isolated serial / parallel ports for expansion boards
Display
2 x 40 character LCD
Host communications
10 /100 Base T Ethernet
UDP and TCP/IP protocols
Loop communications
Five fiber optic TX/RX ports (10 Mbit/sec)
Power input
+24 VDC (+/-2 V), 500 mA.