PSI System Controls and Diagnostics
A500 User Manual
A500_UM_090115 Page 47 of 61
16
Gate-Counter Option Board
16.1 Overview
The gate-counter is a full-size I/O board which connects to both expansion port connectors of the
cell controller board. It is logically connected on port 1. JPR B3 on bank 2 on the cell controller
is fitted to identify the board.
The gate-counter provides the same function as the gate option board and adds a ten-channel
pulse scaler facility. The pulse inputs are designed to detect NIM-standard double height fast
logic pulses (-1.6 V, >= 5 nsec duration). The input impedance is 50 ohms, so the nominal input
drive current is 32 mA.
16.2 Circuit description
The incoming signals (negative going) are terminated in 50 ohms and sent to one input of a fast
comparator. The other input of the comparator is set to threshold voltage by a buffered voltage
divider. The nominal threshold setting is -0.45 V, and this is common to all ten inputs.
The comparator outputs are connected to a dedicated FPGA which provides ten parallel 32 bit
counters. This communicates with the cell controller over multiple serial interfaces. When the
cell controller asserts a control line, all ten counters are zeroed and start to acquire data. When
the selected integration time is reached, the gate-counter FPGA interrupts the cell controller DSP
which executes a readout sequence. The counter contents are copied and latched, and the
counters are reset. There is no interruption to the counting. The cell controller reads the counts
over the serial data lines in the background.
The minimum integration time is 100 µsec. There is no upper limit, but you must not risk
counter overflow, so a maximum of 60 sec is recommended. The maximum count is 2^32, or
about 4.3e9 counts. In general you should choose integration times that will give a few hundred
counts for typical anticipated rates, so as to achieve a reasonable compromise between time
resolution and counting statistics.
In any integration readout, there is a resolution of 5 individual counts. However no individual
counts are lost, so this quickly becomes negligible over multiple integrations. As an example,
say there was a constant input of 30 kHz, and 100 µsec integrations. The expected count in each
integration would thus be 3. The reported counts would be 0, 5, 5, 10, 15, 15, 20 etc. Generally
such low counts should be avoided, however, by using appropriate integration periods, because
the otherwise the counting statistics are poor.
