PSI System Controls and Diagnostics
A500 User Manual
A500_UM_090115 Page 48 of 61
-5 V
Gnd
50R
FPGA
Vref
I/P 1
I/P 10
Data out to
cell controller
Data in from
cell controller
Control lines
Figure 24. Counter circuit simplified schematic
16.3 Operation of the Counter Function Using the PTC Diagnostic
The PSI Diagnostic host program allows you to try out the counter inputs. Figure 25 shows the
setup tab arranged so that the counters are triggered by a positive-going edge on gate input 3/C.
The counters will be read out 100 times in continuous succession, with individual integration
times of 1 msec.