PSI System Controls and Diagnostics
A500 User Manual
A500_UM_090115 Page 44 of 61
14
POST
The boot-loader starts up the A500 by performing a Power On Self Test (POST), checking the
integrity of the A500. The results are displayed on the LCD. The following tests are performed
in sequence:
Device
Description
Display
Write the alphabet to the right hand portion of the display. The user can verify
that this occurs.
NVR
The battery-backed up non-volatile RAM is given a non-destructive test that
writes different patterns to each locations and verifies the write. Sequential
values are also written to make sure that the value stays written. No check of
the actual battery persistence is made, since this would require that the
controller be powered off.
SRAM
The external SRAM is checked by walking a bit through all memory
locations, and also by writing sequential values and verifying. This is a
destructive test, and all memory is set to 0 upon completion.
FLASH
The flash memory is tested first by examination of the factory sequence 0x20
and 0x17 that is found at location 0 of the FLASH. The reserved POST block
(63) is then used to write out a sequence of 0xAAAA, 0x5555, 0x0000, and
0xFFFF and an ascending sequence and read back. This is a destructive test,
but is done on only the reserved segment.
Watchdog
The watchdog is tested by first writing a special value to the NVR, then by
holding off the watchdog tickle so that the device resets. If it resets, the boot-
loader knows to vector right back to where it left off, seamlessly testing the
watchdog. If it does not reset after a time-out, a POST error is flagged.
Timer
The FPGA timer is tested by measuring the timer versus the DSP timer for 1
second.
Ethernet
A special test message is transmitted to the RCM3200 or A30 Ethernet
processor and read back to determine if the Ethernet board is operating
properly. The IP address of the A500 is displayed on the LCD. No test is
made to determine if host communications are working.