PSI System Controls and Diagnostics
A500 User Manual
A500_UM_090115 Page 33 of 61
Ethernet
processor
Sharc DSP
FPGA
App code
Flash
SRAM
NVR
DC-DC
converters
24VDC
in
LCD
Interface board
Gate input (4)
Communication
Fibre-optic loops
Cell controller board
Boot
Flash
I/O Port
I/O Port
FPGA
Counter input (10)
Network
Figure 18. A500-R5T5-GC schematic architecture
10.3 State machine
The A500 obeys a state machine as shown in figure 19.