31
TSP-16
5
6
7
8
5
6
7
8
A
B
C
D
E
F
IN/OUT
Pull-up Setting
Pin No.
Select Function
Signal Name
Description
Normal
Operation
During
Reset
Internal
External
J19
eim.EIM_DATA29 EIM_D1
3
U
S
B IC CONTROL
IO
Input
PU
(100K)
J20
eim.EIM_DATA
3
0 EIM_D14 U
S
B IC CONTROL
IO
Input
PU
(100K)
H21
eim.EIM_DATA
3
1 EIM_D15 U
S
B IC CONTROL
IO
Input
PD
(100K)
E22
eim.EIM_EB2
EIM_XBEH
BT_CFG4[6]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PD15k
F2
3
eim.EIM_EB
3
EIM_xBEL
BT_CFG4[7]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PD15k
N22 gpio6.GPIO6_IO
3
1 NC
UNU
S
ED
O(L)
Output
0
M25
eim.EIM_DTACK_B
EIM_xDACK
BT_CFG4[1]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PD15k
K21 src.
S
RC_BOOT_CFG27 BT_CFG4[
3
] BOOT
MODE
S
ETTING PIN
I
Output
1
PD15k
K2
3
src.
S
RC_BOOT_CFG2
8
BT_CFG4[4] BOOT
MODE
S
ETTING PIN
I
Output
1
PD15k
L20 src.
S
RC_BOOT_CFG00 BT_CFG1[0] BOOT
MODE
S
ETTING PIN
I
Input
PU
(100K)
PU4.7k
J25
eim.EIM_AD01
EIM_A1
BT_CFG1[1]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PU4.7k
L21
eim.EIM_AD02
EIM_A2
BT_CFG1[2]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PD14.7k
K24
eim.EIM_AD0
3
EIM_A
3
BT_CFG1[
3
]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PD14.7k
L22
eim.EIM_AD04
EIM_A4
BT_CFG1[4]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PD14.7k
L2
3
eim.EIM_AD05
EIM_A5
BT_CFG1[5]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PD14.7k
K25
eim.EIM_AD06
EIM_A6
BT_CFG1[6]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PU4.7k
L25
eim.EIM_AD07
EIM_A7
BT_CFG1[7]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PU4.7k
L24
eim.EIM_AD0
8
EIM_A
8
BT_CFG2[0]
U
S
B IC CONTROL
BOOT MODE
S
ETTING PIN
O Input PU
(100K)
PD14.7k
M21 src.
S
RC_BOOT_CFG09 BT_CFG2[1] BOOT
MODE
S
ETTING PIN
I
Input
PU
(100K)
PU4.7k
M22 src.
S
RC_BOOT_CFG10 BT_CFG2[2] BOOT
MODE
S
ETTING PIN
I
Input
PU
(100K)
PD14.7k
M20 src.
S
RC_BOOT_CFG11 BT_CFG2[
3
] BOOT
MODE
S
ETTING PIN
I
Input
PU
(100K)
PU4.7k
M24 src.
S
RC_BOOT_CFG12 BT_CFG2[4] BOOT
MODE
S
ETTING PIN
I
Input
PU
(100K)
PD14.7k
M2
3
src.
S
RC_BOOT_CFG1
3
BT_CFG2[5] BOOT
MODE
S
ETTING PIN
I
Input
PU
(100K)
PD14.7k
N2
3
src.
S
RC_BOOT_CFG14 BT_CFG2[6] BOOT
MODE
S
ETTING PIN
I
Input
PU
(100K)
PD14.7k
N24 src.
S
RC_BOOT_CFG15 BT_CFG2[7] BOOT
MODE
S
ETTING PIN
I
Input
PU
(100K)
PD14.7k
V20
enet.ENET_MDC ENET_MDC
LAN
CONTROL O
Input
PU
(100K)
V2
3
enet.ENET_MDIO ENET_MDIO
LAN
CONTROL IO
Input
PU
(100K)
PU1.5k
U21
enet.ENET_RX_EN ENET_CR
S
_DV LAN
CONTROL
I
Input
PU
(100K)
V22 gpio1.GPIO1_IO2
3
NC
UNU
S
ED O(L)
Input
PU
(100K)
W2
3
enet.ENET_RX_ER ENET_RX_ER
LAN
CONTROL I
Input
PU
(100K)
PU10k
V21
enet.ENET_TX_EN ENET_TX_EN
LAN
CONTROL O
Input
PU
(100K)
W21
enet.ENET_RX_DATA0 ENET_RXD0
LAN
CONTROL I
Input
PU
(100K)
W22
enet.ENET_RX_DATA1 ENET_RXD1
LAN
CONTROL I
Input
PU
(100K)
U20
enet.ENET_TX_DATA0 ENET_TXD0
LAN
CONTROL O
Input
PU
(100K)
W20
enet.ENET_TX_DATA1 ENET_TXD1
LAN
CONTROL O
Input
PU
(100K)
T5 gpio1.GPIO1_IO00
NC
(U
S
BPWR_EN) UNU
S
ED (U
S
B_H1 port)
O
Input
PD
(100K)
T4
usb.U
S
B_OTG_ID U
S
B_OTG_ID
U
S
B_OTG_ID INPUT
L : Host control H : Device control
I Input
PU
(100K)
PD4.7k
T1
usdhc2.
S
D2_WP
S
D_WP
S
D CARD CONNECTION FOR DEBUGGING
(Normal mode : L output fixed)
O(L) Input PU
(47K)
R7 gpio1.GPIO1_IO0
3
NC
(U
S
BPWR_OC) UNU
S
ED (U
S
B_H1 port)
I
Input
PU
(100K)
R6
usdhc2.
S
D2_CD_B
S
D_DET
S
D CARD CONNECTION FOR DEBUGGING
(Normal mode : L output fixed)
O(L) Input PU
(47K)
R4 gpio1.GPIO1_IO05
MIDI_PA
SS
MIDI THROUGH
S
ELECT
L : OFF H : ON
O Input PU
(100K)
T
3
gpio1.GPIO1_IO06
S
EL_U
S
B_OTG_ID
U
S
B_OTG CONTROL PORT
S
ELECT
L : Host control H : Device control
O Input PU
(100K)
PD4.7k
R
3
uart2.UART2_TX_DATA MIDI_OUT
MIDI
OUT
S
IGNAL O
Input
PU
(100K)
PD22k
(Digi Tr)
R5
uart2.UART2_RX_DATA MIDI_IN
MIDI
IN
S
IGNAL I
Input
PU
(100K)
PU270
T2 gpio1.GPIO1_IO09
NC
(wdog1)
UNU
S
ED (wdog1/Check needle)
O(L) Input PU (100K)
R2
enet.ENET_REF_CLK ENET_REF_CLK
LAN CONTROL
O
Input
PU
(100K)
R1 gpio7.GPIO7_IO12
CLK_CONT
AUDIO CLK POWER
S
UPPLY
V+
3
R
3
D_CLK CONTROL
L : POWER OFF H : POWER ON
O(L) Input PU (100K)
PD4.7k
P6 gpio7.GPIO7_IO1
3
PMIC_xINT
PMIC
CONTROL I
Input
PU
(100K)
PU6
8
k
P5 gpio4.GPIO4_IO05
NC
(AUTH_xR
S
T) UNU
S
ED (Authentication IC Control)
O
Input
PU
(100K)
PD10k
W5 gpio4.GPIO4_IO06
NC
UNU
S
ED/Check needle
O (L)
Input
PU
(100K)
V6 gpio4.GPIO4_IO07
NC
UNU
S
ED O
(L)
Input
PU
(100K)
U7 gpio4.GPIO4_IO0
8
NC
(AUD) UNU
S
ED/Check needle
O (L)
Input
PU
(100K)
U6 gpio4.GPIO4_IO09
NC
(AUD)
UNU
S
ED/Check needle
O (L)
Input
PU
(100K)
W6 gpio4.GPIO4_IO10
NC
(U
S
B) UNU
S
ED (U
S
B_H1 port)
O (L)
Input
PU
(100K)