PIONEER DJ TSP-16, Руководство по обслуживанию

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35
TSP-16
5 6 7 8
5 6 7 8
A
B
C
D
E
F
IN/OUT Pull-up Setting
Pin No. Select Function Signal Name Description
Normal
Operation
During
Reset
Internal External
D10 U S B_H1_VBU S NC(U S B_H1_VBU S ) UNU S ED (U S B_H1 port)/Check needle I
E9 U S B_OTG_VBU S V+5R1D U S B_OTG_VBU S INPUT I
F9 VDD_U S B_CAP V+ 3 R0_VDDU S B IMX POWER S UPPLY (U S B_CAP) PWR PWR
G9 VDD_ S NV S _CAP V+*R*VDD_ S NV S _CAP IMX POWER S UPPLY ( S NV S _CAP) PWR PWR
H10 VDD_HIGH_CAP V+2R5VPH IMX POWER S UPPLY (HIGH_CAP) PWR PWR
J10 VDDHIGH_CAP V+2R5VPH IMX POWER S UPPLY (HIGH_CAP) PWR PWR
H17 VDD_PU_CAP V+1R2_VDDPU_CAP IMX POWER S UPPLY (PU_CAP) PWR PWR
J17 VDD_PU_CAP V+1R2_VDDPU_CAP IMX POWER S UPPLY (PU_CAP) PWR PWR
K17 VDD_PU_CAP V+1R2_VDDPU_CAP IMX POWER S UPPLY (PU_CAP) PWR PWR
L17 VDD_PU_CAP V+1R2_VDDPU_CAP IMX POWER S UPPLY (PU_CAP) PWR PWR
M17 VDD_PU_CAP V+1R2_VDDPU_CAP IMX POWER S UPPLY (PU_CAP) PWR PWR
N17 VDD_PU_CAP V+1R2_VDDPU_CAP IMX POWER S UPPLY (PU_CAP) PWR PWR
P17 VDD_PU_CAP V+1R2_VDDPU_CAP IMX POWER S UPPLY (PU_CAP) PWR PWR
R10 VDD S OC_CAP V+1R1_VDD S OC_CAP IMX POWER S UPPLY ( S OC_CAP) PWR PWR
T10 VDD S OC_CAP V+1R1_VDD S OC_CAP IMX POWER S UPPLY ( S OC_CAP) PWR PWR
T1 3 VDD S OC_CAP V+1R1_VDD S OC_CAP IMX POWER S UPPLY ( S OC_CAP) PWR PWR
T14 VDD S OC_CAP V+1R1_VDD S OC_CAP IMX POWER S UPPLY ( S OC_CAP) PWR PWR
U10 VDD S OC_CAP V+1R1_VDD S OC_CAP IMX POWER S UPPLY ( S OC_CAP) PWR PWR
U1 3 VDD S OC_CAP V+1R1_VDD S OC_CAP IMX POWER S UPPLY ( S OC_CAP) PWR PWR
U14 VDD S OC_CAP V+1R1_VDD S OC_CAP IMX POWER S UPPLY ( S OC_CAP) PWR PWR
H11 VDD_ARM2 3 _CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
H1 3 VDD_ARM_CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
J11 VDD_ARM2 3 _CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
J1 3 VDDARM_CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
K11 VDD_ARM2 3 _CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
K1 3 VDDARM_CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
L11 VDD_ARM2 3 _CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
L1 3 VDDARM_CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
M11 VDD_ARM2 3 _CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
M1 3 VDDARM_CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
N11 VDD_ARM2 3 _CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
N1 3 VDDARM_CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
P11 VDD_ARM2 3 _CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
P1 3 VDDARM_CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
R11 VDD_ARM2 3 _CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
R1 3 VDDARM_CAP V+1R2_VDDARM_CAP IMX POWER S UPPLY (ARM_CAP) PWR PWR
A4 GND GND GND GND GND
A 8 GND GND GND GND GND
A1 3 GND GND GND GND GND
A25 GND GND GND GND GND
B4 GND GND GND GND GND
C1 GND GND GND GND GND
C4 GND GND GND GND GND
C6 GND GND GND GND GND
C10 GND GND GND GND GND
D 3 GND GND GND GND GND
D6 GND GND GND GND GND
D 8 GND GND GND GND GND
E5 GND GND GND GND GND
E6 GND GND GND GND GND
E7 GND GND GND GND GND
F5 GND GND GND GND GND
F6 GND GND GND GND GND
F7 GND GND GND GND GND
F 8 GND GND GND GND GND
G 3 GND GND GND GND GND
G10 GND GND GND GND GND
G19 GND GND GND GND GND
H 8 GND GND GND GND GND
H12 GND GND GND GND GND
H15 GND GND GND GND GND
H1 8 GND GND GND GND GND
J2 GND GND GND GND GND
J 8 GND GND GND GND GND
J12 GND GND GND GND GND
J15 GND GND GND GND GND