33
TSP-16
5
6
7
8
5
6
7
8
A
B
C
D
E
F
IN/OUT
Pull-up Setting
Pin No.
Select Function
Signal Name
Description
Normal
Operation
During
Reset
Internal
External
U
3
LVD
S
0_DATA1_P LVD
S
0_TX1_P LCD
CONTROL(LVD
S
)
O
Input
Keeper
V2 LVD
S
0_DATA2_N LVD
S
0_TX2_N LCD
CONTROL(LVD
S
)
O
—
—
V1 LVD
S
0_DATA2_P LVD
S
0_TX2_P LCD
CONTROL(LVD
S
)
O
Input
Keeper
V4 LVD
S
0_CLK_N LVD
S
0_CLK_N LCD
CONTROL(LVD
S
)
O
—
—
V
3
LVD
S
0_CLK_P LVD
S
0_CLK_P LCD
CONTROL(LVD
S
)
O
Input
Keeper
W2 LVD
S
0_DATA
3
_N NC
(LVD
S
0_TX
3
_N) UNU
S
ED (LVD
S
0_TX
3
port)
—
—
W1 LVD
S
0_DATA
3
_P NC
(LVD
S
0_TX
3
_P) UNU
S
ED (LVD
S
0_TX
3
port)
Input
Keeper
Y1 LVD
S
1_DATA0_N NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
—
—
Y2 LVD
S
1_DATA0_P NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
Input
Keeper
AA2 LVD
S
1_DATA1_N NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
—
—
AA1 LVD
S
1_DATA1_P NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
Input
Keeper
AB1 LVD
S
1_DATA2_N NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
—
—
AB2 LVD
S
1_DATA2_P NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
Input
Keeper
Y
3
LVD
S
1_CLK_N NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
—
—
Y4 LVD
S
1_CLK_P NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
Input
Keeper
AA
3
LVD
S
1_DATA
3
_N NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
—
—
AA4 LVD
S
1_DATA
3
_P NC
(LVD
S
1) UNU
S
ED (LVD
S
1
port)
Input
Keeper
B21
ecspi5.EC
S
PI5_MO
S
I iMX_IDAC_MO
S
I IDAC
CONTROL
O(L)
Input
PU
(100K)
D20
ecspi5.EC
S
PI5_
S
CLK iMX_IDAC_
S
CLK IDAC
CONTROL
O(L)
Input
PU
(100K)
A21 gpio1.GPIO1_IO16
NC
EC
S
PI5
S
TANDBY/Check needle
O(L)
Input
PU
(100K)
C20
ecspi5.EC
S
PI5_
SS
0 iMX_IDAC_xC
S
IDAC
CONTROL
O(L)
Input
PU
(100K)
E19
pwm2.PWM2_OUT LCD_PWM
LCD BACKLIGHT LUMINANCE CONTROL
O Input PU
(100K)
PD4.7k
F1
8
gpio1.GPIO1_IO21
NC
EC
S
PI5
S
TANDBY/Check needle
O(L)
Input
PU
(100K)
F19
usdhc2.
S
D2_CMD
S
D_CMD
S
D CARD CONNECTION FOR DEBUGGING
(Normal mode : L output fixed)
O(L) Input PU
(47K)
C21
usdhc2.
S
D2_CLK
S
D_CLK
S
D CARD CONNECTION FOR DEBUGGING
(Normal mode : L output fixed)
O(L) Input PU
(47K)
A22
usdhc2.
S
D2_DATA0
S
D_DATA0
S
D CARD CONNECTION FOR DEBUGGING
(Normal mode : L output fixed)
IO Input PU
(47K)
E20
usdhc2.
S
D2_DATA1
S
D_DATA1
S
D CARD CONNECTION FOR DEBUGGING
(Normal mode : L output fixed)
IO Input PU
(47K)
A2
3
usdhc2.
S
D2_DATA2
S
D_DATA2
S
D CARD CONNECTION FOR DEBUGGING
(Normal mode : L output fixed)
IO Input PU
(47K)
B22
usdhc2.
S
D2_DATA
3
S
D_DATA
3
S
D CARD CONNECTION FOR DEBUGGING
(Normal mode : L output fixed)
IO Input PU
(47K)
B1
3
usdhc
3
.
S
D
3
_CMD eMMC_CMD
eMMC
CONTROL
O
Input
PU
(47K)
PU4.7k
D14
usdhc
3
.
S
D
3
_CLK eMMC_CLK
eMMC
CONTROL
O
Input
PU
(47K)
E14
usdhc
3
.
S
D
3
_DATA0 eMMC_DATA0
eMMC
CONTROL
IO
Input
PU
(47K)
PU47k
F14
usdhc
3
.
S
D
3
_DATA1 eMMC_DATA1
eMMC
CONTROL
IO
Input
PU
(47K)
PU47k
A15
usdhc
3
.
S
D
3
_DATA2 eMMC_DATA2
eMMC
CONTROL
IO
Input
PU
(47K)
PU47k
B15
usdhc
3
.
S
D
3
_DATA
3
eMMC_DATA
3
eMMC
CONTROL
IO
Input
PU
(47K)
PU47k
D1
3
usdhc
3
.
S
D
3
_DATA4 eMMC_DATA4
eMMC
CONTROL
IO
Input
PU
(47K)
PU47k
C1
3
usdhc
3
.
S
D
3
_DATA5 eMMC_DATA5
eMMC
CONTROL
IO
Input
PU
(47K)
PU47k
E1
3
usdhc
3
.
S
D
3
_DATA6 eMMC_DATA6
eMMC
CONTROL
IO
Input
PU
(47K)
PU47k
F1
3
usdhc
3
.
S
D
3
_DATA7 eMMC_DATA7
eMMC
CONTROL
IO
Input
PU
(47K)
PU47k
D15
usdhc
3
.
S
D
3
_RE
S
ET eMMC_xR
S
T eMMC
CONTROL
O
Input
PU
(47K)
PD4.7k
PU47k
E16
gpmi.NAND_WE_B NANDF_WE_B NAND
FLA
S
H CONTROL
O
Input
PU
(100K)
B17
gpmi.NAND_RE_B NANDF_RE_B NAND
FLA
S
H CONTROL
O
Input
PU
(100K)
D1
8
gpio2.GPIO2_IO0
8
NC
UNU
S
ED O(L)
Input
PU
(100K)
B19 gpio2.GPIO2_IO09
NC
UNU
S
ED O(L)
Input
PU
(100K)
F17 gpio2.GPIO2_IO10
NC
UNU
S
ED O(L)
Input
PU
(100K)
A20 gpio2.GPIO2_IO11
NC
UNU
S
ED O(L)
Input
PU
(100K)
E1
8
gpio2.GPIO2_IO12
NC
UNU
S
ED O(L)
Input
PU
(100K)
C19 gpio2.GPIO2_IO1
3
ENET_ETHER_INT
LAN
CONTROL I
Input
PU
(100K)
PU10k
B20 gpio2.GPIO2_IO14
ENET_xR
S
T LAN
CONTROL
O
Input
PU
(100K)
PD10k
D19 gpio2.GPIO2_IO15
NC
UNU
S
ED O(L)
Input
PU
(100K)
B
8
U
S
B_OTG_CHD_B U
S
B_OTG_CHD_B (TP)
UNU
S
ED/Check
needle
—
—
B6 U
S
B_OTG_DN U
S
B_OTG_DN U
S
B
S
IGNAL
(OTG)
IO
—
—
A6 U
S
B_OTG_DP U
S
B_OTG_DP U
S
B
S
IGNAL
(OTG)
IO — —
E10 U
S
B_H1_DP U
S
B_H1_DP UNU
S
ED (U
S
B_H1port)/Check
needle
IO — —
F10 U
S
B_H1_DN U
S
B_H1_DN UNU
S
ED (U
S
B_H1port)/Check
needle
IO
—
—
H14 VDD_ARM_IN
V+1R
3
75CORE IMX
POWER
S
UPPLY
(ARM_IN)
J14 VDDARM_IN
V+1R
3
75CORE IMX
POWER
S
UPPLY
(ARM_IN)
K9 VDD_ARM2
3
_IN V+1R
3
75CORE IMX
POWER
S
UPPLY
(ARM_IN)
K14 VDDARM_IN
V+1R
3
75CORE IMX
POWER
S
UPPLY
(ARM_IN)
L9 VDD_ARM2
3
_IN V+1R
3
75CORE IMX
POWER
S
UPPLY
(ARM_IN)
L14 VDDARM_IN
V+1R
3
75CORE IMX
POWER
S
UPPLY
(ARM_IN)
M9 VDD_ARM2
3
_IN V+1R
3
75CORE IMX
POWER
S
UPPLY
(ARM_IN)