PIONEER DJ TSP-16, Руководство по обслуживанию

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37
TSP-16
5 6 7 8
5 6 7 8
A
B
C
D
E
F
AC10 DRAM_ S DQ S3 _P MDQ S3 DDR 3 CONTROL O Input Hi-Z
AB10 DRAM_ S DQ S3 _N MDQ S3 _N DDR 3 CONTROL O — —
AE10 DRAM_DQM 3 MDQM 3 DDR 3 CONTROL O Output 0
AA17 DRAM_DATA 3 2 NC (DRAM) UNU S ED (DRAM port) O(L) Input PU (100K)
AA1 8 DRAM_DATA 33 NC (DRAM) UNU S ED (DRAM port) O(L) Input PU (100K)
AC1 8 DRAM_DATA 3 4 NC (DRAM) UNU S ED (DRAM port) O(L) Input PU (100K)
AE19 DRAM_DATA 3 5 NC (DRAM) UNU S ED (DRAM port) O(L) Input PU (100K)
Y17 DRAM_DATA 3 6 NC (DRAM) UNU S ED (DRAM port) O(L) Input PU (100K)
Y1 8 DRAM_DATA 3 7 NC (DRAM) UNU S ED (DRAM port) O(L) Input PU (100K)
AB19 DRAM_DATA 38 NC (DRAM) UNU S ED (DRAM port) O(L) Input PU (100K)
IN/OUT Pull-up Setting
Pin No. Select Function Signal Name Description
Normal
Operation
During
Reset
Internal External
AB 3 GND GND GND GND GND
AB24 GND GND GND GND GND
AD4 GND GND GND GND GND
AD7 GND GND GND GND GND
AD10 GND GND GND GND GND
AD1 3 GND GND GND GND GND
AD16 GND GND GND GND GND
AD19 GND GND GND GND GND
AD22 GND GND GND GND GND
AE1 GND GND GND GND GND
AE25 GND GND GND GND GND
C14 S ATA_REXT NC ( S ATA) UNU S ED ( S ATA port)
G12 S ATA_VPH GND ( S ATA) UNU S ED ( S ATA port)
G1 3 S ATA_VP GND ( S ATA) UNU S ED ( S ATA port)
N12 VDD_CACHE_CAP V+1R1_VDD S OC_CAP IMX POWER S UPPLY ( S OC_CAP) PWR PWR
AD2 DRAM_DATA00 MDQ0 DDR 3 CONTROL IO Input PU (100K)
AE2 DRAM_DATA01 MDQ1 DDR 3 CONTROL IO Input PU (100K)
AC4 DRAM_DATA02 MDQ2 DDR 3 CONTROL IO Input PU (100K)
AA5 DRAM_DATA0 3 MDQ 3 DDR 3 CONTROL IO Input PU (100K)
AC1 DRAM_DATA04 MDQ4 DDR 3 CONTROL IO Input PU (100K)
AD1 DRAM_DATA05 MDQ5 DDR 3 CONTROL IO Input PU (100K)
AB4 DRAM_DATA06 MDQ6 DDR 3 CONTROL IO Input PU (100K)
AE4 DRAM_DATA07 MDQ7 DDR 3 CONTROL IO Input PU (100K)
AE 3 DRAM_ S DQ S 0_P MDQ S 0 DDR 3 CONTROL O Input Hi-Z
AD 3 DRAM_ S DQ S 0_N MDQ S 0_N DDR 3 CONTROL O — —
AC 3 DRAM_DQM0 MDQM0 DDR 3 CONTROL O Output 0
AD5 DRAM_DATA0 8 MDQ 8 DDR 3 CONTROL IO Input PU (100K)
AE5 DRAM_DATA09 MDQ9 DDR 3 CONTROL IO Input PU (100K)
AA6 DRAM_DATA10 MDQ10 DDR 3 CONTROL IO Input PU (100K)
AE7 DRAM_DATA11 MDQ11 DDR 3 CONTROL IO Input PU (100K)
AB5 DRAM_DATA12 MDQ12 DDR 3 CONTROL IO Input PU (100K)
AC5 DRAM_DATA1 3 MDQ1 3 DDR 3 CONTROL IO Input PU (100K)
AB6 DRAM_DATA14 MDQ14 DDR 3 CONTROL IO Input PU (100K)
AC7 DRAM_DATA15 MDQ15 DDR 3 CONTROL IO Input PU (100K)
AD6 DRAM_ S DQ S 1_P MDQ S 1 DDR 3 CONTROL O Input Hi-Z
AE6 DRAM_ S DQ S 1_N MDQ S 1_N DDR 3 CONTROL O — —
AC6 DRAM_DQM1 MDQM1 DDR 3 CONTROL O Output 0
AB7 DRAM_DATA16 MDQ16 DDR 3 CONTROL IO Input PU (100K)
AA 8 DRAM_DATA17 MDQ17 DDR 3 CONTROL IO Input PU (100K)
AB9 DRAM_DATA1 8 MDQ1 8 DDR 3 CONTROL IO Input PU (100K)
Y9 DRAM_DATA19 MDQ19 DDR 3 CONTROL IO Input PU (100K)
Y7 DRAM_DATA20 MDQ20 DDR 3 CONTROL IO Input PU (100K)
Y 8 DRAM_DATA21 MDQ21 DDR 3 CONTROL IO Input PU (100K)
AC 8 DRAM_DATA22 MDQ22 DDR 3 CONTROL IO Input PU (100K)
AA9 DRAM_DATA2 3 MDQ2 3 DDR 3 CONTROL IO Input PU (100K)
AD 8 DRAM_ S DQ S 2_P MDQ S 2 DDR 3 CONTROL O Input Hi-Z
AE 8 DRAM_ S DQ S 2_N MDQ S 2_N DDR 3 CONTROL O — —
AB 8 DRAM_DQM2 MDQM2 DDR 3 CONTROL O Output 0
AE9 DRAM_DATA24 MDQ24 DDR 3 CONTROL IO Input PU (100K)
Y10 DRAM_DATA25 MDQ25 DDR 3 CONTROL IO Input PU (100K)
AE11 DRAM_DATA26 MDQ26 DDR 3 CONTROL IO Input PU (100K)
AB11 DRAM_DATA27 MDQ27 DDR 3 CONTROL IO Input PU (100K)
AC9 DRAM_DATA2 8 MDQ2 8 DDR 3 CONTROL IO Input PU (100K)
AD9 DRAM_DATA29 MDQ29 DDR 3 CONTROL IO Input PU (100K)
AD11 DRAM_DATA 3 0 MDQ 3 0 DDR 3 CONTROL IO Input PU (100K)
AC11 DRAM_DATA 3 1 MDQ 3 1 DDR 3 CONTROL IO Input PU (100K)