38
TSP-16
1
2
3
4
A
B
C
D
E
F
1
2
3
4
IN/OUT
Pull-up Setting
Pin No.
Select Function
Signal Name
Description
Normal
Operation
During
Reset
Internal
External
AC19
DRAM_DATA
3
9 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AD1
8
DRAM_
S
DQ
S
4_P NC
(DRAM) UNU
S
ED
(DRAM
port)
Input
Hi-Z
AE1
8
DRAM_
S
DQ
S
4_N NC
(DRAM) UNU
S
ED
(DRAM
port)
—
—
AB1
8
DRAM_DQM4 NC
(DRAM)
UNU
S
ED
(DRAM
port)
O(L)
Output
0
Y19
DRAM_DATA40 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AB20
DRAM_DATA41 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AB21
DRAM_DATA42 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AD21
DRAM_DATA4
3
NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
Y20
DRAM_DATA44 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AA20
DRAM_DATA45 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AE21
DRAM_DATA46 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AC21
DRAM_DATA47 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AD20
DRAM_
S
DQ
S
5_P NC
(DRAM) UNU
S
ED
(DRAM
port)
Input
Hi-Z
AE20
DRAM_
S
DQ
S
5_N NC
(DRAM) UNU
S
ED
(DRAM
port)
—
—
AC20
DRAM_DQM5 NC
(DRAM)
UNU
S
ED
(DRAM
port)
O(L)
Output
0
AC22
DRAM_DATA4
8
NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AE22
DRAM_DATA49 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AE24
DRAM_DATA50 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AC24
DRAM_DATA51 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AB22
DRAM_DATA52 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AC2
3
DRAM_DATA5
3
NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AD25
DRAM_DATA54 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AC25
DRAM_DATA55 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AD2
3
DRAM_
S
DQ
S
6_P NC
(DRAM) UNU
S
ED
(DRAM
port)
Input
Hi-Z
AE2
3
DRAM_
S
DQ
S
6_N NC
(DRAM) UNU
S
ED
(DRAM
port)
—
—
AD24
DRAM_DQM6 NC
(DRAM)
UNU
S
ED
(DRAM
port)
O(L)
Output
0
AB25
DRAM_DATA56 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AA21
DRAM_DATA57 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
Y25
DRAM_DATA5
8
NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
Y22
DRAM_DATA59 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AB2
3
DRAM_DATA60 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AA2
3
DRAM_DATA61 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
Y2
3
DRAM_DATA62 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
W25
DRAM_DATA6
3
NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Input
PU
(100K)
AA25
DRAM_
S
DQ
S
7_P NC
(DRAM) UNU
S
ED
(DRAM
port)
Input
Hi-Z
AA24
DRAM_
S
DQ
S
7_N NC
(DRAM) UNU
S
ED
(DRAM
port)
—
—
Y21
DRAM_DQM7 NC
(DRAM)
UNU
S
ED
(DRAM
port)
O(L)
Output
0
AC14
DRAM_ADDR00 MA0
DDR
3
CONTROL
O
Output
0
AB14
DRAM_ADDR01 MA1
DDR
3
CONTROL
O
Output
0
AA14
DRAM_ADDR02 MA2
DDR
3
CONTROL
O
Output
0
Y14
DRAM_ADDR0
3
MA
3
DDR
3
CONTROL
O
Output
0
W14
DRAM_ADDR04 MA4
DDR
3
CONTROL
O
Output
0
AE1
3
DRAM_ADDR05 MA5
DDR
3
CONTROL
O
Output
0
AC1
3
DRAM_ADDR06 MA6
DDR
3
CONTROL
O
Output
0
Y1
3
DRAM_ADDR07 MA7
DDR
3
CONTROL
O
Output
0
AB1
3
DRAM_ADDR0
8
MA
8
DDR
3
CONTROL
O
Output
0
AE12
DRAM_ADDR09 MA9
DDR
3
CONTROL
O
Output
0
AA15
DRAM_ADDR10 MA10
DDR
3
CONTROL
O
Output
0
AC12
DRAM_ADDR11 MA11
DDR
3
CONTROL
O
Output
0
AD12
DRAM_ADDR12 MA12
DDR
3
CONTROL
O
Output
0
AC17
DRAM_ADDR1
3
MA1
3
DDR
3
CONTROL
O
Output
0
AA12
DRAM_ADDR14 MA14
DDR
3
CONTROL
O
Output
0
Y12
DRAM_ADDR15 NC
(DRAM) UNU
S
ED
(DRAM
port)
O(L)
Output
0
AC15
DRAM_
S
DBA0 MBA0 DDR
3
CONTROL
O
Output
0
Y15
DRAM_
S
DBA1 MBA1 DDR
3
CONTROL
O
Output
0
AB12
DRAM_
S
DBA2 MBA2 DDR
3
CONTROL
O
Output
0
Y16
DRAM_C
S
0 MC
S
0 DDR
3
CONTROL
O
Output
0
AD17
DRAM_C
S
1 NC
(DRAM)
UNU
S
ED
(DRAM
port)
O(L)
Output
0
AB15
DRAM_RA
S
MRA
S
DDR
3
CONTROL
O
Output
0
AE16
DRAM_CA
S
MCA
S
DDR
3
CONTROL
O
Output
0
AB16
DRAM_
S
DWE MWE DDR
3
CONTROL
O
Output
0
Y11
DRAM_
S
DCKE0 MCKE0
DDR
3
CONTROL
O
Output
0
AA11
DRAM_
S
DCKE1 NC
(DRAM) UNU
S
ED (DRAM port)
O(L)
Output
0
AC16
DRAM_ODT0 MODT0 DDR
3
CONTROL
O
Output
0
AB17
DRAM_ODT1 NC
(DRAM)
UNU
S
ED
(DRAM
port)
O
Output
0
Y6
DRAM_RE
S
ET MR
S
T DDR
3
CONTROL
O
Output
0
PD10k
AD15
DRAM_
S
DCLK0_P MCK0
DDR
3
CONTROL
O
Input
Hi-Z
AE15
DRAM_
S
DCLK0_N MCK0_N
DDR
3
CONTROL
O
—
—
AD14
DRAM_
S
DCLK1_P MCK1
DDR
3
CONTROL
O
Input
Hi-Z
AE14
DRAM_
S
DCLK1_N MCK1_N
DDR
3
CONTROL
O
—
—
