Peritek VCD-V, Руководство пользователя

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Peritek
General Information 1-13
VMEbus Access:
All device registers (34020, color map(s), DUARTs, PC
Keyboard port, High Speed Port, and SCSI) and on-board
memory are accessible to the bus through a 1K byte
window in the A16 I/O space which uses the 16-bit Line
Address Register (LAR).
The Line Buffer may also be located in A24 space if the
host CPU only supports A16/D16. Best performance results
if the VMEbus address space supports D32 transfers.
Contact Peritek if you need to use this mode.
An optional direct A32 address mapping gives a 64 MB
window into board memory. Except for PX Windows when
used in a multi-processor environment, Peritek software
does not use the A32 addressing feature.
Control Registers: The graphics board has a four register block in the A16
space which contains the Control Status Register (CSR),
Line Address Register (LAR), Line Buffer Address
Register, Extended Address Register, and Interrupt Vector
Address Register.
VMEbus Interrupts: VMEbus interrupt controller supports a vectored interrupt
from the 34020.
Bus Loading: Two bus loads
Data Strobe to DTACK: Times were measured using an HP1650A logic analyzer at
the VME P1 connector, using 1000 test cycles. The 34020
was halted. The host CPU was a Motorola MVME162.
Depending on the host, you need to add about 150 ns of
VMEbus overhead to get the total cycle time. The long
maximum access time is due to access during a memory
refresh cycle.
Assuming 150 ns VMEbus overhead, write transfer rates
will be about 12.7 MB/s, and read transfer rates will be
about 6.2 MB/s (when doing long word accesses).
34020 arbitrated accesses: Write: min: 140 ns Read: min: 420 ns
max: 1.2 us max: 2.0 us
average: 168 ns average: 497 ns