Peritek VCD-V, Руководство пользователя

Страница: 147 / 183

Peritek
Programming On-board Devices and Memories 5-51
As described in Section 4.2, on some versions of the VCD-V, instead of
the GAL16V8 circuit described in the previous paragraph, an ICS1562
programmable pixel clock generator supplies pipeline reset, differential
ECL level dot clock and load clock for the BT459 and the VRAM shift
clock.
The details of the internal control registers are documented in the BT459
data sheet.
Table 5-29 BT459 registers
VMEbus
Offset Mnemonic Function
3 CMAPARL Low byte of BT459 address register. Two bit low
order internal counter addresses individual R, G,
and B locations when color maps are accessed.
(See description above).
7 CMAPARH High byte of BT459 address register. See
description above.
B CSRMAP BT459 control/status buffer, cursor position
control and bit map, zoom control, and cursor
and overlay color maps.
F PRIPAL Primary plane color map palette. 256 x 3 (R,G,B)
locations. R,G,B locations cycled by mod-3
counter.