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5-14 Programming On-board Devices and Memories
5.3 TMS 34020 Graphics Systems Processor
The Texas Instruments 34020 Graphics System Processor (GSP) is a
general-purpose, 32-bit programmable processor with specialized
graphics instructions and a 512 byte LRU instruction cache. It includes a
full set of video timing control registers. The 34020 has a 32-bit processor
data (LAD) bus which is connected directly to the 34082 FPU and to a set
of two 74BCT16652 16-bit bus transceivers which act as buffers between
the low drive capability LAD bus and the high load memory/device
(MAD) bus.
A 34020's 32-bit host address bus and 34020 to VMEbus data multiplexers
support a low latency interface between the VMEbus and the 34020,
memory, and devices. The 34020 takes care of arbitration and data and
address bus control for the host interface. Commands, status, display
parameters, graphics drawing, refresh, and display update address data are
all passed over these common busses.
The 34020 operates on memory in byte, word or long word segments. It
also supports page-mode read and write memory accesses for maximum
memory performance. For graphics memory, color register, block fill and
writemask functions are supported. The writemask operation is write
enable per bit enable function which allows direct writes instead of read-
modify-writes).
The 34020 derives its timing from a clock which is independent of the
video clock. In fact, the standard clock is 40 MHz, while the typical video
clock is 110 MHz. The 34020 has internal synchronizers which take care
of VRAM memory accesses (CPU clock synchronous) and VRAM shift,
load, and blank functions (video clock synchronous). The 34020 has inputs
for the VRAM shift and load clocks so that it can keep track of blanking
even with horizontal zoom enabled. Section 4.2 covers the high speed
clock and zoom generation.
An interesting consequence of the dual clock nature of the 34020 is that if
you read a register driven by the pixel clock (e.g. VCOUNT), you will get
erratic results. You have to read the comparison flag or use interrupts to
get correct results. The reason for this is simple: the VCOUNT register can
change state in the middle of a 34020 read cycle. Its operations are totally
asynchronous to the 34020 CPU clock.
The purpose of this section is to supplement the well written and already
complete information provided in the 34020 User's Guide, especially in
the areas which relate to display timing and memory interface. The 34020