Peritek VCD-V, Руководство пользователя

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Peritek
Programming On-board Devices and Memories 5-53
5.9 BT482 - Color Map Controller for the VCD-V
Note
This section describes the features of the BT482. Some of these features
are not directly used or supported in the Peritek
PX Windows including
overlays (but this will change with X11R6).
The BT482 color map/cursor controller is used in VCD-V configurations
(e.g. VCD-V/X6/D8) which include the digital lookup table (DLUT) and a
desire for medium resolution analog output. In most other cases the BT459
will be used (see Section 5.8). Since the BT482 only latches one pixel at a
time and the VRAM array is arranged 4 pixels wide, it is fed by the DLUT
pixel multiplexer. Once the pixel is clocked into the BT482, it is processed
like the BT459, except there is no blink function.
The BT482 provides composite sync generation, the color map lookup
tables, cursor bit map and position control, primary and overlay plane
blinking and blanking, and video output DACs. In addition to the
customary 256 word translation map for the 8-bit primary graphics plane,
it contains 15 additional table entries for the 4-bit graphics overlay planes
and 3 for the 2-bit cursor. Each table entry is a 24 bit value (8 bits each for
R, G, and B).
The BT482 has a two bit graphics cursor. It contains a 32 x 32 x 2 bit map,
position match registers, and counters triggered by the dot clock and
referenced to horizontal and vertical sync. The match registers compare a
programmed value (corresponding to an X-Y position on the screen) to the
counters. When coincidence occurs, the cursor output become active and
select one of the three cursor colors. By setting the correct internal control
bits, the BT482 can supply a bit-map cursor and/or a cross-hair cursor. The
display window for the cross-hair is programmable.
A four bit horizontal zoom control is taken from the MACH110 VCDV6
and applied to the load inputs of a GAL16V8-7 (VCDV9) which functions
as a high speed counter to yield an integer zoom function at 125 MHz.
VCDV9 also generates a differential TTL clock and load for the BT482.
Using the clock from the GAL, VCDV6 generates VCLK for the 34020
and VRAM shift clocks.
As described in section 4.2, on some versions of the VCD-V, instead of
the GAL16V8 circuit described in the previous paragraph, an ICS1562
programmable pixel clock generator supplies pipeline reset, TTL level dot
clock and load clock for the BT482 and the VRAM shift clock.