Peritek VCD-V, Руководство пользователя

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Peritek
5-44 Programming On-board Devices and Memories
BT463). Pseudo color is supported by the BT463, but not in Peritek's
software. See the BT463 data sheet for more information.
As mentioned above, the BT463 supports a 4-bit overlay. Pixel
intersections between any of the planes results in a unique color, so that
the pixels will still be visible. This is because the overlay has a higher
priority than the primary input in selecting an output color value. In other
words, as long as the data bits going into the overlay inputs are
NON-
ZERO , they will select a color for a particular pixel position.
Setting control bit CR12 in command register 1 splits the 4-bit overlay
plane into overlay/underlay mode. When CR12 is set and for any given
pixel bit 3 of the overlay plane is clear, then the lower three bits of the
overlay plane actually define an underlay color.
There are additional control inputs to the BT463 which, when used in
conjunction with bits in the BT463 command register, support switching
between true and pseudo color modes on pixel boundaries. These bits are
called the window type bits. They permit the simultaneous existence of
several windows on the screen, each with its own color map, either true or
pseudo color. For a complete description of how these bits work, see the
BT463 data sheet.
The BT463 has twenty internal registers plus the window type table and
the color palette RAM. They are accessed via a four single byte
register/data buffer group programmed through the device buffer
(VCTLAR = 400). Each byte is located on a
long-word boundary. The
first two bytes make a 12 bit address register. Byte 3 is the data buffer for
register and window type table (REGDBR) and byte 4 is the data buffer for
the color map (PALET)
The BT463 is controlled through an 8 bit I/O port. It is addressed
indirectly, with the use of an address register, followed by three data
registers. In order to make loading of the BT463 as fast as possible, the
address register autoincrements after each access to one of the data buffer
bytes. In the case of access to control registers, the address register
increments after each access. When accessing the window type table,
cursor colors, or color palette RAM, two additional low order address bits
are used. They are internal only and are cleared by a read or write to the
address register. The low two bits count mod-3, and thus cycle through the
R, G, and B parts of each of the 256 LUT entries. Only after these bits
have cycled will the main address register increment. Access to the
window-type table should be restricted to vertical and horizontal blanking
times. Note that the new values to be loaded into the color map location
are actually loaded when the blue value is loaded. The red and green