Peritek
Programming On-board Devices and Memories
5-67
register called the Target Command Register, which is used to select the
SCSI control lines when the SCSI port is used in "target" mode. This
register can also be used in our application: the expected phase (command
or data, input or output, message or not) can be loaded into this register by
the SCSI driver. If at any time the phase does not match, the 5380 will
generate a
non-maskable
interrupt and clear the phase match bit in the
Bus Status Register. This can be used to determine the end of a SCSI
transaction, or to indicate an error (if the phase changes unexpectedly).
One should be careful to never enter a protocol state only on the basis of
the C/D, I/O and Message lines. REQ must be set prior to entering the next
state.
Pseudo DMA Data Transfers can be used to significantly improve data
transfer times. Ordinarily, the 34020 has to test the REQ* and ACK* bits
to transfer data. By putting the 5380 into DMA mode when transferring
data, some of the bit toggling will be assumed by the 5380 itself. Set bit 1
in the MDR, poll bit 6 (DRQ) in the Bus & Status Register and when
active, read or write data as required to the Pseudo DMA Data Buffer
(LAR 800, offset 0 or 34020 address C100 0000). DMA transfers are
initiated by writing (anything) to the correct DMA start register.
While the SCSI chip is intended to control SCSI devices, it makes a fine
parallel I/O port too. In this case, the CSD/ODR register would be used for
passing 8-bits of data. Depending on whether you have the 5380
programmed as a target or initiator, other control bits can be used as
handshaking bits. Consult the 5380 data sheet for detailed information.
Table 5-39 SCSI Register Initialization
Offset
Read/Write
Value
Mnemonic
Function
183
Read
--
CSD
Current SCSI Data
Write
data out
ODR
Output Data Register
187
Yes
0
ICR
Initiator Command
18B
Yes
0
MDR
Mode Register
18F
Yes
0
TCR
Target Command Register
193
Read
--
CSB
Current SCSI Bus Status
Write
1
SER
Select Enable Register
197
Read
--
BSR
Bus & Status Register
19B
Read
data in
IDR
Input Data Register
19F
Read
--
RIR
Reset Interrupt Register
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