Panasonic FP-M Hardware, Руководство пользователя

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192
8-5. System Registers
Address
402
403
Name of system register
Pulse catch input function
settings
(pulse of 500 µs or more
duration)
Interrupt trigger settings
Default
value
H0
H0
Description
This register specifies the pulse catch inputting function
availabilities for X0 to X7.
• Settings
0: standard input mode
1: pulse catch input mode
Input the specific value in an order so that the bit
corresponding to each input becomes “1” when you use the
pulse catch function.
• Setting range
All FP-Ms (8 inputs X0 to X7): H0 to HFF
EXAMPLE:
If the pulse catch function is used for inputs X3, X4, and
X5, input H38 as follows:
This register specifies inputs of the FP-M as interrupt
triggers.
• Settings
0: standard input mode
1: interrupt input mode
Input the specific value in an order so that the bit
corresponding to each input becomes “1” when you use
interrupt programs.
• Setting range
All FP-Ms (8 inputs X0 to X7): H0 to HFF
EXAMPLE:
If the interrupt input function is used for inputs X1 and X2,
input H6 as follows:
Bit position 7 4
• •
X7 X4 X6 X5
Corresponding
input
3 0
• •
11 8
• •
15 12
• •
X3 X0 X2 X1
System register 403
6
Bit position
Corresponding
input
Data input 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
7 4
• •
X7 X4 X6 X5
3 0
• •
11 8
• •
15 12
• •
X3 X0 X2 X1
System register 403
Bit position 7 4
• •
X7 X4 X6 X5
Corresponding
input
3 0
• •
11 8
• •
15 12
• •
X3 X0 X2 X1
System register 402
H
Bit position
Corresponding
input
Data input 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0
3 8
7 4
• •
X7 X4 X6 X5
3 0
• •
11 8
• •
15 12
• •
X3 X0 X2 X1
H
System register 402