Omega Engineering OMB-CHARTSCAN 1400, Руководство пользователя

Страница: 231 / 273

Registers, Data Formats, & Queries Appendix C
C-14 ChartScan User’s Manual
Calibration Status Register (
U2 Command
)
The calibration status register indicates which calibration errors, if any have occurred. The individual errors are
described in the
U2
command. Any calibration error will be mapped into the Calibration Status which maps to
the Calibration Error bit in the Error Source Register.
Error Source Register
(E? Command)
The error source register indicates which errors, if any, have occurred. The individual errors are described in
the
E?
command.
When an error occurs, it sets the appropriate bit in the error source register. This in turn sets a bit in the event
status register as shown in the previous figure.
Event Status Register
The event status register is read with the
U0
command. The contents of the register are cleared after the
U0
command is satisfied. The event status register indicates which events, if any, have occurred. Its bits, and the
event that set them, are as follows:
Bit No. Event Set/Clear Information
0 Acquisition
Complete? Set when acquisition operation has been completed. An acquisition is
complete when the acquisition device has finished the current
acquisition. The bit will be cleared when a new acquisition is configured
through the T command.
1 Stop Event
Set when the pre-trigger count specified in the trigger configuration (by
the T command) has been satisfied. This bit is cleared when a new
acquisition is configured either through the Trigger Configuration (T)
command or when the unit is rearmed via the auto-rearm mode.
2 Query Error Set when the controller has attempted to read from the acquisition
device when:
(a) no response is present or pending, or
(b) a response has been lost because the controller has sent a new
query before reading the response to a prior query.
3 Device
Dependent
Error Set when a conflict error has occurred. A conflict error is generated
when a command cannot execute correctly because it would interfere
with other commands or settings.
4 Execution Error Set when one of several errors has occurred during the execution of a
command.
5 Command
Error Set when a command syntax error is detected.
6 75% Limit
Exceeded
Set when the Acquisition Buffer has been filled to at least 75% of its
capacity. The bit is cleared when the amount of data in the Acquisition
Buffer falls below 75% of its capacity.
7 Power On Set on power-on or system reset (*R).
Event Status Enable Register
The event status enable register controls which events, if any, are to be reflected in the status byte register. As
shown in the following figure, the bits of the event status register are logically ANDed with the corresponding
bits of the event status enable register. The resulting bits are logically ORed together in the status byte register.
Note that the event status enable register does not affect the event status register; it only affects the ESB bit of
the status byte register. The event status enable register is set and interrogated with the Nn command.