NXP Semiconductors SAFE ASSURE FRDMGD3100HBIEVM, Руководство пользователя, Страница: 34 / 35

NXP Semiconductors
UM11134
FRDMGD3100HBIEVM half-bridge evaluation board
UM11134 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2020. All rights reserved.
User guide Rev. 3 — 10 February 2020
34 / 35
Tables
Tab. 1. Device features ................................................. 5
Tab. 2. Low-voltage (LV) domain 24-pin connector
definitions .......................................................... 7
Tab. 3. Driver board test point definitions ......................8
Tab. 4. Power related jumper definitions .....................10
Tab. 5. Signal related jumper configurations ............... 12
Tab. 6. Interrupt LED definitions ..................................16
Tab. 7. Translator board jumper functionality .............. 18
Tab. 8. Translator board test point definition ............... 18
Figures
Fig. 1. FRDMGD3100HBIEVM ..................................... 1
Fig. 2. Connecting FRDM-KL25Z, GD3100 half-
bridge EVB and translator board .......................6
Fig. 3. Evaluation board voltage and interface
domains .............................................................7
Fig. 4. Key test point locations .....................................8
Fig. 5. Power supply and jumpers configuration .........10
Fig. 6. Signal related jumper locations ....................... 12
Fig. 7. GD3100 evaluation board bottom view ........... 14
Fig. 8. Gate drive resistors .........................................15
Fig. 9. LED interrupt indicators ...................................16
Fig. 10. Freedom Development Platform ..................... 17
Fig. 11. Logic translator board ..................................... 17
Fig. 12. Evaluation board and system setup ................ 20
Fig. 13. FRDM-KL25Z setup and interface ...................22
Fig. 14. SPIGen general view ...................................... 24
Fig. 15. Mode registers and GPIO controls view ..........25
Fig. 16. Configuration registers view ............................25
Fig. 17. Status, mask, and REQADC registers view .....26
Fig. 18. Pulse test view ................................................27
Fig. 19. Daisy chain view ............................................. 27
Fig. 20. Single command view ..................................... 28
Fig. 21. Batch commands view .................................... 29