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NXP Semiconductors

UM11134

FRDMGD3100HBIEVM half-bridge evaluation board

UM11134

All information provided in this document is subject to legal disclaimers.

User guide

Rev. 3 — 10 February 2020

31 / 35

Problem

Evaluation

Explanation

Corrective action(s)

Check position of VEEx_SEL (J1, J2)

jumpers

VEEx_SEL jumpers set the VCC/VEE

potential relative to each HV domain

GND

Disable HV domain power supplies,

and set correct VEExSEL jumpers.

See

Section 4.4.3.2

for details.

Clear VCCOV bit (STATUS1) to

continue.

Check solder joint integrity of VEEx_

SEL (J1, J2) jumpers and other

VEEx-GNDISOx components

VEEx_SEL jumper (J1, J2) short

between 2-3, or low-impedance

component failure can cause VCC-

VEE potential to exceed VCCOV

Remove power.
Check VEEx_SEL jumper integrity.

Remove jumper and apply continuity

check for 2-3 short.
Check that Zener diode regulator is

valid in diode check.

VCCOV fault reported on startup

Check VCC-GNDISO potential

PWM is disabled during a VCC

overvoltage (20 V nom.)

Tune VCC-GNDISO potential to

suitable level with power supply set

resistor (R20).
Clear VCCOV bit (STATUS1) to

continue.

No PWM during short circuit test

Check PWMxSEL jumpers

Incorrect configuration of PWMALT

pins prevent short-circuit test by

enforcing dead time

For short-circuit test, set PWMLSEL

(J31) and PWMHSEL (J32) to bypass

dead time. See

Section 4.4.4.2

for

details.

Check VSUP/VDD for undervoltage

condition

VDD_UV latches SPI buffer contents,

preventing updated fault reporting.

Check voltage provided at VDD pin

(pin 3).
On each read, compare the address

from the sent command and response

(a difference indicates that the SPI

response is latched due to inactive).

Read multiple addresses to ensure a

good comparison.

Check VCC is enabled at PS_EN

(J25) jumper

PS_EN can be enabled/disabled in

hardware or software

Enable VCC/VEE from SPIGen.
If using Rev B translator, set PS_EN

(J25) to 2-3 to permanently enable

the supply.

Bad SPI data, appears to repeat

previous response

Check VCC for undervoltage

Unpowered VCC prevents HV domain

from updating data

Tune VCC-GNDISO using R20

feedback

7 Schematics, board layout and bill of materials

The board schematics, board layout and bill of materials are available at

http://

www.nxp.com/FRDMGD3100HBIEVM

on the Overview tab under Get Started.

8 References

Following are URLs where you can obtain information on related NXP products and

application solutions:

NXP.com support pages

Description

URL

FRDMGD3100HBIEVM

Tool summary page

http://www.nxp.com/FRDMGD3100HBIEVM

GD3100

Product summary page

http://www.nxp.com/GD3100

Содержание SAFE ASSURE FRDMGD3100HBIEVM

Страница 1: ...UM11134 FRDMGD3100HBIEVM half bridge evaluation board Rev 3 10 February 2020 User guide 1 FRDMGD3100HBIEVM Figure 1 FRDMGD3100HBIEVM ...

Страница 2: ...hnical support services Should this evaluation kit not meet the specifications indicated in the kit it may be returned within 30 days from the date of delivery and will be replaced by a new kit NXP reserves the right to make changes without further notice to any products herein NXP makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose no...

Страница 3: ... the Jump To navigation feature on the left side of the window 3 Select the Get Started link 4 Review each entry in the Get Started section 5 Download an entry by clicking on the linked title After reviewing the Overview tab visit the other related tabs for additional information Documentation Download current documentation Software Tools Download current hardware and software tools Buy Parametric...

Страница 4: ...uation board The kit includes the Freedom KL25Z microcontroller hardware for interfacing a PC installed with SPIGen software for communication to the SPI registers on the GD3100 gate drive devices in either daisy chain or standalone configuration The GD3100 translator board is used to translate 3 3 V signals to 5 0 V signals between the MCU and GD3100 gate drivers The evaluation kit can be connect...

Страница 5: ...ignal isolation Integrated gate drive power stage capable of 15 A peak source and sink Interrupt pin for fast response to faults Compatible with negative gate supply Complimentary PWM PWMALT controls for dead time insertion Independent fail safe enable and fail safe state controls Compatible with 200 V to 1700 V IGBTs power range 125 kW 4 4 Board description The FRDMGD3100HBIEVM is a half bridge e...

Страница 6: ...0 February 2020 6 35 Figure 2 Connecting FRDM KL25Z GD3100 half bridge EVB and translator board 4 4 1 Low voltage logic and controls connector Low voltage domain is 12 V VSUP VPWR domain that interfaces with the MCU and GD3100 control registers through the 24 pin connector interface Low side driver and high side driver domains are driver control interfaces to IGBT single phase connections and test...

Страница 7: ...ed signal low side 2 n c No connection 3 CSBL Chip select bar low side 4 n c No connection 5 PWML PWM input low side 6 INTBL Interrupt bar low side 7 MOSIL Master out slave in low side 8 SCLK Serial clock input 9 MISOL Master in slave out low side 10 EN_PS Enable power supplies for VCC VEE 11 FSSTATEL Fail safe state low side 12 GND Ground 13 FSENB Fail safe enable high side and low side 14 MISOH ...

Страница 8: ...nts are clearly marked on the evaluation board Figure 4 shows the location of various test points Figure 4 Key test point locations Table 3 Driver board test point definitions Test point Reference designator Definition Low voltage LV domain VSUP TP2 DC voltage source connection point for VSUP power input of GD3100 devices and flyback power supplies Typically supplies by vehicle battery 12 V DC but...

Страница 9: ...int Connected to low side IGBT emitter COLL J27 Two post header provides direct access to measure VCE for low side IGBT High side HS driver domain VCCH TP1 Provides access to measure positive voltage supply powering HV die and gate driver for high side IGBT VRFH TP3 Monitor internal 5 0 V reference for analog circuitry on HV isolated die TSENSEH TP4 Input for high side IGBT temperature measurement...

Страница 10: ...osed VDD VSUP connected VDD internal regulator bypassed Device powered by external 5 0 V Open VCC regulator VCCREG active gate driver GH uses VCCREG default VCCL J6 Closed VCC regulator VCCREG disabled gate driver GH uses VCC 1 2 VEE is negative supply default 2 3 VEE is tied to IGBT emitter GNDISOL VEEL_SEL J2 Open Not allowed VCC and VEE float relative to IGBT emitter GNDISOL Open VDD VSUP are s...

Страница 11: ...figure GD3100 for 5 0 V power short VDD to VSUP provide 5 0 V to VSUP connection Short VDDH J29 jumper Short VDDL J6 jumper Connect 5 0 V to VSUP TP2 4 4 3 2 Configuring VEE for gate drive GL To configure for negative VEE provided by onboard zener network default Connect VEEH_SEL J1 jumper to 1 2 Connect VEEL_SEL J2 jumper to 1 2 VEE for high side provided by Zener D2 and bias resistors R2 R3 VEE ...

Страница 12: ...r supplies always enabled MCU control signal is disconnected default PS_EN J25 Open Passive pulldown R14 disables VCC VEE power supplies 1 2 Separate CSBH and CSBL Use for normal mode default 2 3 CSBH and CSBL tied together Use for daisy chain CSB J34 Open Not allowed Only CSBL will be active not recommended for normal use 1 2 MISOL is passed directly to MCU Use for normal SPI mode default 2 3 MIS...

Страница 13: ...ow along with steps to adapt the driver board are described The jumper functionalities are detailed in Table 5 4 4 4 1 SPI configuration options To configure for normal SPI low and high side GD3100s are addressable separately default Set CSB J34 jumper to 1 2 Set MISO J35 jumper to 1 2 Short MOSI J30 jumper From SPIGen SPI0 addresses low side GD3100 U4 with CSBL use SPI1 to address high side GD310...

Страница 14: ...e the power supplies 4 4 5 Bottom view Figure 7 GD3100 evaluation board bottom view 4 4 6 Gate drive resistors RGH gate high resistor in series with the GH pin at the output of the GD3100 high side driver and IGBT gate that controls the turn on current for IGBT gate RGL gate low resistor in series with the GL pin at the output of the GD3100 low side driver and IGBT gate that controls the turn off ...

Страница 15: ...D interrupt indicators Interrupt LEDs are provided to visually alert the user of a reported fault The LEDs are supplied with 3 3 V from the KL25Z and are driven directly by the INTB pin of the respective GD3100 device A 220 Ω resistor is used for current limiting D14 INTBH LED is ON while fault is being reported INTB low LED is OFF while no fault is reported INTB high D25 INTBL LED is ON while fau...

Страница 16: ... designator Description Low side INTB D25 Connected to the INTB output pin active low of low side GD3100 LED is ON indicates reported fault check system LED is OFF indicates no reported fault High side INTB D14 Connected to the INTB output pin active low of high side GD3100 LED is ON indicates reported fault check system LED is OFF indicates no reported fault 4 5 Kinetis KL25Z freedom board The Fr...

Страница 17: ... the MCU and the GD3100 driver board The driver board is exposed to high voltage and may require 3 3 V or 5 0 V logic necessitating an interface board Various signals like the SPI communication interrupt fail safe controls and PWM pass through the translator board The translator board provides a configurable output voltage 3 3 V or 5 0 V going out to the GD3100 driver board The translator board al...

Страница 18: ...T_PWML TP10 PWML signal provided to driver board EXT_PWMH TP11 PWMH signal provided to driver board GND TP12 GND connection for translator also connected to GND on LV domain of driver board The translator board in FRDMGD3100HBIEVM supports different configurations for various application tests The translator supports PWM from either the KL25Z see Section 4 6 1 Configuring the translator for KL25Z ...

Страница 19: ... USB power bus that is pinned out to the translator for this purpose To configure the translator board to send receive 5 0 V logic level signals perform the following 1 Set VCCSEL J233 jumper to 1 2 4 6 4 Configuring the translator for 3 3 V logic operation This configuration is for use with the 3 3 V gate driver device MC33GD3100A3EK populated on the driver board The attached KL25Z has a 3 3 V re...

Страница 20: ... SPI communication and pass PWM signals to evaluate working operation 5 2 2 Intended audience Experienced engineers evaluating GD3100 gate drive device for IGBT control 5 2 3 Setting up and connecting the evaluation kit 1 Download and Install latest SPIGEN software Windows application from NXP com to your PC see Section 6 2 Configuring the FRDM KL25Z microcode 2 Assemble the FRDMGD3100HBIEVM with ...

Страница 21: ...SPI communication can be conducted with GD3100 devices over SPIGen as described in Section 6 3 Using the SPIGEN graphical user interface See GD3100 data sheet for additional details a Selecting SPI0 communicates with low side gate drive device and SPI1 communicates with high side gate drive device see Figure 14 8 Apply PWM signals to each gate drive Gate drive output can be observed on high side a...

Страница 22: ... drivers overwrites any previous SPIGen installation and replaces it with a current version containing the GD3100 drivers However configuration files spi from the previous version remain intact 6 2 Configuring the FRDM KL25Z microcode By default the FRDM KL25Z with this kit is preprogrammed with the current and most up to date firmware available for the kit A way to quickly check that the microcod...

Страница 23: ...EVM 7 With the KL25Z still plugged through the OpenSDA port copy drag and drop the srec file into the KL25Z device memory Once done disconnect the USB and plug into the other USB port labeled KL25Z a The device may not appear as a distinct device to the computer while connected through the KL25Z USB port this is normal 8 The FRDM KL25Z board is now fully set up to work with FRDMGD3100HBIEVM and th...

Страница 24: ... send identical back to back commands so the response is obtained upon a single click of the Read button This is normal SPI operation but is implemented this way for the end user s convenience On Daisy Chain view only one READ operation is performed per click Two READ operations must be performed to obtain response data On all views WRITE operations are only performed once per click 6 3 1 Mode reg...

Страница 25: ...egisters and GPIO controls view 6 3 2 Configuration register See GD3100 data sheet for configuration SPI register descriptions When attempting to change configuration parameters ensure the CONFIG_EN bit in the MODE2 register is set to 1 READ operations send identical back to back commands so the response is obtained upon a single click of the Read button WRITE operations are only performed once pe...

Страница 26: ...uide Rev 3 10 February 2020 26 35 6 3 3 Status and mask register See GD3100 data sheet for status and mask SPI register descriptions INTB indicators mirror the status of the INTB pin on both high side and low side GD3100 simultaneously but only one either high side or low side can be read at a time over SPI selected by SPI 0 or SPI 1 in this view Figure 17 Status mask and REQADC registers view ...

Страница 27: ...Section 4 4 4 2 Configuring dead time application in hardware so the desired pulse is not distorted by the dead time protection For a repeating PWM waveform provided by a timer pin on the KL25Z use the PWM Controls to define frequency and duty cycle The duty cycle is referenced to PMWH for example when duty cycle is set at 80 PWMH 80 PWML 20 Figure 18 Pulse test view 6 3 5 Daisy chain When FRDMGD3...

Страница 28: ... from any tab are logged here in hexadecimal and can be saved and exported in a text file Daisy chain length command structure n 24 bit length where n 1 are not supported by this view Figure 20 Single command view 6 3 7 Batch command The Batch commands view allows creation of scripts containing commands defined by the Single command page Batches can be named saved and recalled This is useful for q...

Страница 29: ...translator board revision Check firmware version in SPIGen according to Figure 14 Match this to microcode needed for translator board revision stated in Section 6 2 step 6 Check PWM control signal Ensure that proper PWM signal is reaching GD3100 Monitor EXT_PWML TP10 and EXT_PWMH TP11 for commanded PWM state Check FSENB status see GD3100 pin 15 STATUS3 PWM is disabled when FSENB L Set pin FSENB H ...

Страница 30: ...On initialization watchdog fault is reported when one die is powered up before the other Check VSUP and VCC both have power applied Clear WDOG_FLT bit STATUS2 to continue SPIERR reported on startup Check KL25Z translator connection On initialization SPIERR can occur when the SPI bus is open or when GD3100 IC is powered up before the translator which provides CSB Clear SPIERR fault to continue Rein...

Страница 31: ... Incorrect configuration of PWMALT pins prevent short circuit test by enforcing dead time For short circuit test set PWMLSEL J31 and PWMHSEL J32 to bypass dead time See Section 4 4 4 2 for details Check VSUP VDD for undervoltage condition VDD_UV latches SPI buffer contents preventing updated fault reporting Check voltage provided at VDD pin pin 3 On each read compare the address from the sent comm...

Страница 32: ...ion B Global various figures tables updated to support new translator board revision C Section 5 2 updated text Section 6 2 added SPIGen installation procedure Section 6 1 added firmware installation procedure Section 6 3 complete rewrite for newest release of SPIGen Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 updated for newest SPIGen v7 2 2 release Figure 20 Figure 21 added as ge...

Страница 33: ...stomer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in ...

Страница 34: ...0HBIEVM 1 Fig 2 Connecting FRDM KL25Z GD3100 half bridge EVB and translator board 6 Fig 3 Evaluation board voltage and interface domains 7 Fig 4 Key test point locations 8 Fig 5 Power supply and jumpers configuration 10 Fig 6 Signal related jumper locations 12 Fig 7 GD3100 evaluation board bottom view 14 Fig 8 Gate drive resistors 15 Fig 9 LED interrupt indicators 16 Fig 10 Freedom Development Pla...

Страница 35: ...2 4 4 4 1 SPI configuration options 13 4 4 4 2 Configuring dead time application in hardware 13 4 4 4 3 Setting method of power supply control VCCx VEEx 13 4 4 5 Bottom view 14 4 4 6 Gate drive resistors 14 4 4 7 LED interrupt indicators 15 4 5 Kinetis KL25Z freedom board 16 4 6 Logic translator board 17 4 6 1 Configuring the translator for KL25Z controlled PWM 18 4 6 2 Configuring the translator ...

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