NXP Semiconductors
UM11134
FRDMGD3100HBIEVM half-bridge evaluation board
UM11134
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User guide
Rev. 3 — 10 February 2020
30 / 35
Problem
Evaluation
Explanation
Corrective action(s)
Check for dead time fault (DTFLT) in
STATUS2 register
Dead time is enforced, but fault
indicates that PWM controls signals
are in violation
Clear DTFLT fault bit (STATUS2).
Check PWMHSEL (J32) and
PWMLSEL (J31) are configured to
bypass dead time faults.
Consider adjusting dead time settings
on GD3100:
•
Change mandatory PWM dead
time setting (CONFIG5)
•
Mask dead time fault (MSK2)
PWM output is good, but with
persistent fault reported
Check for overcurrent (OC) fault in
STATUS1 register
OC fault latches, but does not disable
PWM. OC fault cannot be masked.
Clear OC fault bit (STATUS1).
Adjust OC fault detection settings on
GD3100:
•
Adjust overcurrent threshold
setting (CONFIG1)
•
Adjust overcurrent filter setting
(CONFIG1)
PWM or FSSTATE rising edge has
longer delay than falling edge
Check translator output voltage
versus GD3100 VDD voltage
Low translator output voltage
(compared with correct VDD at
GD3100) causes the logic-high
threshold at the GD3100 pin to be
crossed later than commanded
Check translator output voltage
selection (J233) is configured to the
same level as the GD3100 VDD
Check VCCSEL supply or translator
outputs on the translator board for
excessive loading or supply droop/
pulldown
WDOG_FLT reported on startup
Check VSUP and VCC are powered
On initialization, watchdog fault is
reported when one die is powered up
before the other
Check VSUP and VCC both have
power applied.
Clear WDOG_FLT bit (STATUS2) to
continue.
SPIERR reported on startup
Check KL25Z/translator connection
On initialization, SPIERR can occur
when the SPI bus is open, or when
GD3100 IC is powered up before the
translator (which provides CSB).
Clear SPIERR fault to continue.
Reinitialize power to GD3100 after
translator is powered (over USB).
Check bit length of message sent
There is SPIERR if SCLK does not
see a n*24 multiple of cycles
Use 24-bit message length for SPI
messages
Check CRC
SPIERR faults if CRC provided in
sent message is not good
Use SPIGen to generate commands
with valid CRC. The command can be
copied in binary or hexadecimal and
sent from another program.
SPIERR reported after SPI message
Check for sufficient dead time
between SPI messages
SPIERR fault bit is set when the
time between SPI messages (txfer_
delay) received is too short. Minimum
required delay time is 19 µs.
Check time between CSB rising edge
(old message end) and CSB falling
edge (new message start) during
normal SPI read, and ensure transfer
delay dead time check.
SPIERR can also be cleared in BIST.
VCCREGUV reported on startup
Check VCCREG potential
Caused by low VCC
Clear VCCREGUV fault bit
(STATUS1).
Tune VCC-GNDISO potential with
power supply set resistor (R20).
Check HV domain is powered
correctly
Related to slow rise time of VCC
supply on HV domain, or failed VREF
regulator
Clear VREFUV bit (STATUS2).
Reset HV domain supply if fault bit
does not clear.
VREFUV reported on startup
Check VCC for undervoltage
condition
Low VCC is visible indirectly through
other HV domain faults
Tune VCC-GNDISO using R20
feedback