MPC8349E-mITX-GP Reference Design Platform User’s Guide, Rev. 0
8
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
MPC8349E-mITX-GP Board
Figure 5. DDR SDRAM Connection
1.2.5
Local Bus Controller
The MPC8349E local bus controller has a 32-bit LAD[0–31] address that consists of data multiplex bus
and control signals. The local bus speed is up to 133 MHz. To interface with the standard memory device,
an address latch must provide the address signals. The LALE is used as the latching signal. To reduce the
load of the high speed 32-bit local bus interface, there is a data buffer for all low-speed devices attached
to the memory controller. The on-board single bank 8-Mbyte Flash memory module is connected to the
local bus.
DDR
SDRAM
Controller
V
ref
Generator
V
ref
1.25 V
2.5 V Input
V
ref
DDR
SDRAM
DIMM184
DQ[0:63]
DQM[0:7]
DQS[0:7]
A[0:13], BA[0,1],CTRL
MCK[0:3] pairs
MSYNC_OUT
MSYNC_IN
MPC8349E
VTT
Generator
2.5 V Input
I2C– SCK2
I2C–SDA2
VTT 1.25 V