NXP Semiconductors MPC8349E-mITX-GP, Руководство пользователя, Страница: 25 / 36

MPC8349E-mITX-GP Reference Design Platform User’s Guide, Rev. 0
Freescale Semiconductor 25
Preliminary—Subject to Change Without Notice
MPC8349E-mITX-GP Board
1.6.4.1 Reset Configuration Word SPMF[0–3] and COREPLL[0–6]
CLKIN is the input to the CCB PLL to generate the CCB clock, which provides the platform logic.
Table 16 shows the common combinations of CLKIN, CCB, and the core frequency and their respective
ratios.
18–19 TSEC2M TSEC2 Mode 00 RGMII
01 RTBI
10: Default GMII
10 TBI
20–27 Reserved — Must be cleared
28 TLE True little endian 0: Default Big-endian mode
1 True little endian mode
29 LALE Local Bus ALE
signal timing 0: Default Normal LALE timing
1 LALE is negated 1/2 lbiu_controller_clk earlier.
30 LDP LDP/CKSTP pin
mux state after
reset 0: Default LDP[0] and
LDP[1] = local data parity.
1 LDP[0] = CKSTOP_OUT and LDP[1] =
CKSTOP_IN.
31 Reserved — Must be cleared
Table 16. Core PLL Ratio
CLKIN
SPMF
[0–3]
CCB
CCB
clock:
CLKIN
Ratio
COREPLL
[0–6]
Core
Frequency
CCB Clock:
CLKIN Ratio
66.666 MHz 0101 333 MHz 5:1 00 0010 0 667 MHz 2:1
66.666 MHz 0100 266 MHz 4:1 00 0010 1 667 MHz 2.5:1
66.666 MHz 0011 200 MHz 3:1 00 0010 0 600 MHz 3:1
66.666 MHz 0101 333 MHz 5:1 01 0001 1 500 MHz 1.5:1
66.666 MHz 0100 266 MHz 4:1 00 0010 0 533 MHz 2:1
66.666 MHz 0011 200 MHz 3:1 00 0010 1 500 MHz 2.5:1
66.666 MHz 0101 333 MHz 5:1 00 0001 0 333 MHz 1:1
66.666 MHz 0100 266 MHz 4:1 01 0001 1 400 MHz 1.5:1
66.666 MHz 0011 200 MHz 3:1 01 0010 0 400 MHz 2:1
Table 15. Reset Configuration Word High (RCWH) Bit Descriptions (continued)
Bits Name Meaning Detailed Description