MPC8349E-mITX-GP Reference Design Platform User’s Guide, Rev. 0
Freescale Semiconductor
23
Preliminary—Subject to Change Without Notice
MPC8349E-mITX-GP Board
4–7
SPMF[0–3]
System PLL
multiplication
factor
0110
6:1
0111
7:1
1000
8:1
1001
9:1
1010
10:1
1011
11:1
1100
12:1
1101
13:1
1110
14:1
1111
15:1
8
—
Reserved
Must be cleared.
9–15
COREPLL
[0–6]
Value
coreclk: csb_clk
VCO divider
nn 0000 n
PLL bypassed
PLL bypassed
00 0001 0
1:1
2
01 0001 0
1:1
4
10 0001 0
1:1
8
11 0001 0
1:1
8
00 0001 1
1.5:1
2
01 0001 1
1.5:1
4
10 0001 1
1.5:1
8
11 0001 1
1.5:1
8
00 0010 0: Default
2:1
2
9–15
COREPLL
[0–6]
01 0010 0
2:1
4
10 0010 0
2:1
8
11 0010 0
2:1
8
00 0010 1
2.5:1
2
01 0010 1
2.5:1
4
10 0010 1
2.5:1
8
11 0010 1
2.5:1
8
00 0011 0
3:1
2
01 0011 0
3:1
4
10 0011 0
3:1
8
11 0011 0
3:1
8
16–31
—
Reserved.
Must be cleared.
Table 14. RCWL Bit Descriptions (continued)
Bits
Name
Meaning
Description