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MPC8349E-mITX-GP Reference Design Platform User’s Guide, Rev. 0

Freescale Semiconductor

11

 

Preliminary—Subject to Change Without Notice

MPC8349E-mITX-GP Board

The DS1339 RTC is connected to I

2

C with address 0x68. The software running on PowerPC core can read 

or write to the RTC through the I2C2 interface.

1.2.8

10/100/1000 BaseT Interface

On the MPC8349E-mITX-GP board, GMII mode is used on TSEC1 , which  is connected to the on-board 
10/100/1000 PHY (VSC8201). The TSEC I/O voltage is set to 3.3 V. The GMII (1000 BaseT) is a source 
synchronous bus. For a transmit bus connection, it is synchronous to GTX_CLK from the TSEC module. 
The receive bus connection is synchronous to RX_CLK generated from the PHY device. When the speed 
is 10/100 BaseT (MII), both transmit and receive clocks are generated by the VSC8201 PHY device. The 
MPC8349E MII management interface is connected to the VSC8201 only. 

Figure 7

 shows the connection 

between the MPC8349E TSEC1 to the VSC8201.

Table 4. PCF8574A (U10) Bit Descriptions

PCF8574A 

(U10) bit[0..7]

Name

Read/Write

Description

0

REV1

Read only, write 

has no effect

Board revision number

REV[0:1] definition

00: revision 0.0
01: revision 0.1
10: revision 1.0
11: reserved

1

REV0

2

Reserved

Read only, write 

has no effect

Reserved for future use

3

Reserved

Read only, write 

has no effect

Reserved

4

MPCI_CLKRUN

Read/Write

Reserved

5

PCI_M66EN

Read only, write 

has no effect

PCI M66EN Signal

0: PCI M66EN signal is low, indicates the PCI cards on PCI slot  is 

not 66 MHz capable

1: PCI M66EN signal is high, indicates the PCI cards on PCI slot is 

66 MHz capable

6

BOOT0

Read only, write 

has no effect

Used to determine which Flash is used for boot Flash

0:  Reserved
1: Flash 1 (U7) is the boot Flash

7

Not used

—

—

Содержание MPC8349E-mITX-GP

Страница 1: ...e describes the software that is shipped with the platform Use this manual in conjunction with the following documents MPC8349E PowerQUICC II Pro Integrated Host Processor Family Reference Manual MPC8...

Страница 2: ...ystem 128 MByte unbuffered DIMM SDRAM that is expandable to 1 Gbyte 8 MByte Flash memory one Macronix MX29LV640M Flash memory bankorone ESSI EN29LV640 Flash memory bank Interfaces 10 100 1000 BaseT Et...

Страница 3: ...d in this section are reset interrupts and clock distribution 1 2 1 Reset and Reset Configurations The MPC8349E mITX GP reset module generates a single reset to reset the MPC8349E and other peripheral...

Страница 4: ...vel and this meets the specification of the PORESET input of MPC834x COP JTAG port reset provides convenient hard reset capability for a COP JTAG controller The RESET line is available at the COP JTAG...

Страница 5: ...errupt and connected to IRQ2 of the MPC8349E Therefore the system software can detect the status of the Ethernet link the PHY internal status and the RTC status PCI interrupt PCI_INTA PCI_INTB The 32...

Страница 6: ...the clock distribution on the MPC8349E mITX GP board Figure 4 MPC8349E mITX GP Clock Scheme MPC8349E Local Bus CLK DDR SDRAM CLK LCLKx MCKx DS1339 GND GND 32 768 KHz Crystal MCKx 125 MHz 133 MHz 33 MH...

Страница 7: ...the PCI_SYNC_OUT clock signal which is fed back on the board through the PCI_SYNC_IN signal to the internal system PLL From the power on reset configuration the CSB clock is generated by the internal...

Страница 8: ...ace with the standard memory device an address latch must provide the address signals The LALE is used as the latching signal To reduce the load of the high speed 32 bit local bus interface there is a...

Страница 9: ...rt size The starting address for the Flash bank is 0xFE00_0000 to 0xFE7F_FFFF 1 2 7 I2C The MPC8349E has two I2 C interfaces On the MPC8349E mITX GP board the MPC8349E acts as I2 C master for both I2C...

Страница 10: ...umns the DDR timings e g CAS latency re fresh timing and setup the configuration registers of the MPC8349E DDR memory controller The I2 C address of the DDR SPD EEPROM on I2C2 bus is 0x51 There are tw...

Страница 11: ...and receive clocks are generated by the VSC8201 PHY device The MPC8349E MII management interface is connected to the VSC8201 only Figure 7 shows the connection between the MPC8349E TSEC1 to the VSC820...

Страница 12: ...SB1 a multi port host MPH module and a dual role DR module On the MPC8349E mITX GP board USB1 connects to USB PHY USB3300 through the 8 bit UTMI low pin count interface ULPI The USB3300 PHY connects t...

Страница 13: ...PC8349E JTAG module and is implemented as a set of additional instructions and logic This port can connect to a dedicated emulator for extensive system debugging Several third party emulators in the m...

Страница 14: ...B port emulator is shown in Figure 11 Figure 11 Connecting the MPC8349E mITX GP Board to A Parallel Emulator The 16 pin generic header connector carries the COP JTAG signals and the additional signals...

Страница 15: ...section describes the MPC8349E mITX GP connectors and their pin assignments 1 4 1 Case Connector The case connector J10 connects to the case power switch power LED reset switch PWR_SW can connect to...

Страница 16: ...sts the pin assignments of the COP connector 1 4 3 PCI Slot The MPC8349E mITX GP board has one 32 bit 3 3 V PCI expansion slot P1 for an expansion card WARNING Only the 3 3 V PCI Card is supported Tur...

Страница 17: ...the other for powering a 12 V fan J5 For typical fans the red wire is always positive and the black wire is always negative 1 4 5 Battery Holder The MPC8349E mITX GP board contains an RTC that requir...

Страница 18: ...Is On OFF Jumper Is Off Description A LGPL0 ON 0 000 local bus EEPROM Default 001 I2 C EEPROM PCI_CLK PCI_SYNC_IN 25 44 MHz 010 I2 C EEPROM PCI_CLK PCI_SYNC_IN 25 66 666 MHz 011 Hard coded option 66 M...

Страница 19: ...are write protected Table 9 Lists of Connectors Jumpers Switches and LEDs Reference Description Connectors BT1 Battery holder for RTC J4 Background Debug Mode BDM Header for Flash programming and debu...

Страница 20: ...neous board related data The EEPROM can be write protected by S2 SW3 as shown in Table 11 J19 CPU Power on reset source jumper CPU Power On Reset can be controlled by a hardware MAX811 reset chip jump...

Страница 21: ...odes and endian mode The reset configuration word is divided into reset configuration word lower RCWL and reset configuration word higher RCWH and is loaded from the local bus during the power on or h...

Страница 22: ...Field PCIHOST PCI64 PCI1ABR PCI2ABR COREDIS BMS BOOTSEQ SWEN ROMLOC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field TSEC1M TSEC2M TLE LALE LDP Figure 18 Reset Configuration Word High RCWH Bit Se...

Страница 23: ...0 6 Value coreclk csb_clk VCO divider nn 0000 n PLL bypassed PLL bypassed 00 0001 0 1 1 2 01 0001 0 1 1 4 10 0001 0 1 1 8 11 0001 0 1 1 8 00 0001 1 1 5 1 2 01 0001 1 1 5 1 4 10 0001 1 1 5 1 8 11 0001...

Страница 24: ...ault PCI2 arbiter enabled 3 Reserved Must be cleared 4 COREDIS Core disable mode 0 Default e300 enabled 1 e300 disabled 5 BMS Boot memory space 0 Default 0x0000_0000 0x007F_FFFF 1 0xFF80_0000 0xFFFF_F...

Страница 25: ...1 2 lbiu_controller_clk earlier 30 LDP LDP CKSTP pin mux state after reset 0 Default LDP 0 and LDP 1 local data parity 1 LDP 0 CKSTOP_OUT and LDP 1 CKSTOP_IN 31 Reserved Must be cleared Table 16 Core...

Страница 26: ...se uboot commands There is no change in the SPMF field since 0b0100 is the default value representing the 266 MHz CCB frequency The COREPLL field is changed from the default value of 0b000_0100 repres...

Страница 27: ...core and VI O during ramp up and power down 1 6 6 Chip Select Assignments and Memory Map Table 17 shows an example memory map on the MPC8349E that is used for u boot 1 1 3 in the Flash memory Table 17...

Страница 28: ...ypical Maximum 3 3 V DC 3 0 A 6 5 A 5 0 V DC 300 mA 2 0 A Communication processor MPC8349E running 533 MHz Addressing Total address range Flash memory local bus DDR SDRAM 4 Gbyte 32 address lines Up t...

Страница 29: ...ensions of the MPC8349E mITX GP Board 2 Getting Started This section describes how to boot up the MPC8349E mITX GP board The on board Flash memory has been preloaded with a Flash image from the factor...

Страница 30: ...marked for each reference Using Figure 22 as a guide the default jumper settings are given in Table 19 starting at the left hand top corner of the board and moving around the board in a clockwise mann...

Страница 31: ...ype and various SDRAM configurations and timing parameters WARNING Switch the power OFF when installing removing the DIMM module Figure 23 Installing the DDR1 DIMM Module Both error correcting codes E...

Страница 32: ...Section 2 4 Serial Port Configuration PC 2 3 1 Cable Connections Connect the serial port of the mITX GP system and the personal computer using RS 232 cable supplied with the system Then connect the AC...

Страница 33: ...8 Parity none Number of Stop bits 1 Flow Control Disabled 2 5 Power Up Press the power button on the front panel Figure 25 Front Panel A few seconds after power up the U Boot prompt should be receive...

Страница 34: ...leverages as much BSP elements as possible for all Freescale targets that are supported while offering the flexibility required to customize as necessary components that require platform specific mod...

Страница 35: ...ment describing how to make use of LTIB to build the ISO image 3 1 Third Party Application Software Many third party applications are available for the MPC8349E mITX GP They are typically built on top...

Страница 36: ...roducts are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other...

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