MPC8349E-mITX-GP Reference Design Platform User’s Guide, Rev. 0
4
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
MPC8349E-mITX-GP Board
Figure 2
shows the reset circuitry.
Figure 2. Reset Circuitry of the MPC8349E
•
Hard reset is generated either by the COP/JTAG port or the MPC8349E.
•
Power-on reset is generated by the Maxim MAX811 device. When MR is deasserted and 3.3 V is
ready, the MAX811 internal timeout guarantees a minimum reset active time of 150 ms before
PORESET is deasserted. This circuitry guarantees a 150 ms PORESET pulse width after 3.3 V
reaches the right voltage level, and this meets the specification of the PORESET input of
MPC834x.
•
COP/JTAG port reset provides convenient hard-reset capability for a COP/JTAG controller. The
RESET line is available at the COP/JTAG port connector. The COP/JTAG controller can directly
generate the hard-reset signal by asserting this line low.
•
Push button reset interfaces the MR signal with a debounce capability to produce a manual master
reset of the processor card.
•
Soft reset is generated by the COP/JTAG port. Assertion of SRESET causes the MPC8349E to
abort all current internal and external transactions and set most registers to their default values.
MAX811
3.3 V
MR
Push Button
GND
HRESET from COP
SRESET from COP
TRST from COP
SRESET to MPC8349E
TRST to MPC8349E
PORESET to MPC8349E
FLASH
10/100/1000 PHY
MPC8349E
USB PHYs