NXP Semiconductors MC9S08PA4, Справочное руководство

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3. Update status and control register 1 (ADC_SC1) to select whether conversions will
be continuous or completed only once, and to enable or disable conversion complete
interrupts. The input channel on which conversions will be performed is also selected
here.
15.5.1.2 Pseudo-code example
In this example, the ADC module is set up with interrupts enabled to perform a single 10-
bit conversion at low power with a long sample time on input channel 1, where the
internal ADCK clock is derived from the bus clock divided by 1.
Example: 15.5.1.2.1 General ADC initialization routine
void ADC_init(void)
{
/* The following code segment demonstrates how to initialize ADC by low-power mode,
long
sample time, bus frequency, software triggered from AD1 external pin without FIFO
enabled
*/
ADC_APCTL1 = ADC_APCTL1_ADPC1_MASK;
ADC_SC3 = ADC_SC3_ADLPC_MASK | ADC_SC3_ADLSMP_MASK | ADC_SC3_MODE0_MASK;
ADC_SC2 = 0x00;
ADC_SC1 = ADC_SC1_AIEN_MASK | ADC_SC1_ADCH0_MASK;
}
15.5.2 ADC FIFO module initialization example
Before the ADC module can be used to start FIFOed conversions, an initialization
procedure must be performed. A typical sequence is as follows:
1. Update the configuration register (ADC_SC3) to select the input clock source and the
divide ratio used to generate the internal clock, ADCK. This register is also used to
select sample time and low-power configuration.
2. Update the configuration register (ADC_SC4) to select the FIFO scan mode, FIFO
compare function selection (OR or AND function) and FIFO depth.
3. Update status and control register 2 (ADC_SC2) to select the hardware or software
conversion trigger, compare function options if enabled.
4. Update status and control register 1 (ADC_SC1) to select whether conversions will
be continuous or completed only once, and to enable or disable conversion complete
interrupts. The input channel on which conversions will be performed is also selected
here.
Chapter 15 Analog-to-digital converter (ADC)
MC9S08PA4 Reference Manual, Rev. 5, 08/2017
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